Integrated circuit with frequency-dividing circuits capable of being tested at a high speed

Claim 1

An improved integrated circuit of the type which has a plurality of pins and which includes a frequency-dividing circuit for dividing an input signal, a pulse processing circuit for processing the signal that is divided by said frequency-dividing circuit to produce processed pulses, an output circuit for feeding the processed pulses through at least one first pin to a load, said pulse processing circuit including a reset signal receiving circuit, for discontinuing the transfer of processed pulses to the load following receipt of a reset signal applied to a second pin, and an output buffer circuit connected between said frequency-dividing circuit and a third pin, wherein the improvement comprises: testing means responsive to a test signal applied to said third pin while said reset signal is applied to said second pin for introducing said test signal at an intermediate point in said frequency-dividing circuit, said intermediate point dividing said frequency-dividing circuit into first stage and second stage frequency-dividing circuits, and for permitting transfer of processed pulses to said at least one first pin despite the presence of said reset signal at said second pin, in order to permit testing of said second stage frequency-dividing circuit, said pulse processing circuit, and said output circuit, said testing means including a switching circuit inserted between the first stage and second stage frequency-dividing circuits; test input circuit means having an input connected to said third pin for supplyiing said test signals through said switching circuit to the second stage frequency-dividing circuit; and means included within said output buffer circuit for isolating said output buffer circuit from said third pin when a reset signal is fed through said second pin to said reset signal receiving circuit.