US4418322A
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Automatic digital circuit for synchronizing with a variable baud rate generator
Assignee: TE Connectivity Corp
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Filing: 1982-02-05
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Granted: 1983-11-29
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Expires: 2002-02-05
Abstract
Abstract Electronic switching means for synchronizing a voltage controlled oscillator output with a variable input Baud Rate Clock. A Baud rate counter ratio input to a Phase Lock Loop circuit is selected or electronically switched automatically according to the input signal Baud rate. Binary counters count down a clock during the time an input signal is high, and the result of the count is transferred to an output register which controls, on the basis of the count, the electronic switching of a Baud rate counter to select the appropriate counter ratio output.
Inventors
- 👤 Paul S. Chang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 13:47
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/027; H04L25/00; H04L25/02; H04L25/0262
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
191 words
A digital feedback circuit for synchronizing an oscillator output frequency with a signal input from a variable Baud Rate Clock in order to maintain a fixed input to output frequency ratio, comprising: first binary means connected to a voltage controlled oscillator having an output frequency for counting down at a rate determined by said voltage controlled oscillator output frequency, and having sequentially activated divider outputs for binary division of said output frequency; a system clock generating a system clock signal at a preset bit frequency; second binary means counting down said system clock signal for a period determined by said Baud Rate Clock period; means for registering the count of said second binary counting means logic means responsive to said registering means for selecting an output from said first binary counting means; means for connecting the output of said voltage controlled oscillator to an output terminal; and means for comparing phase differential between said selected output of said first binary counting means and said signal input from said variable Baud Rate Clock and generating a voltage level based upon any phase differential therebetween for adjusting said voltage controlled oscillator output frequency.
Claim 2
Dependent Claim
191 words
A digital feedback circuit for synchronizing an oscillator output frequency with a signal input from a variable Baud Rate Clock in order to maintain a fixed input to output frequency ratio, comprising: first binary means connected to a voltage controlled oscillator having an output frequency for counting down at a rate determined by said voltage controlled oscillator output frequency, and having sequentially activated divider outputs for binary division of said output frequency; a system clock generating a system clock signal at a preset bit frequency; second binary means counting down said system clock signal for a period determined by said Baud Rate Clock period; means for registering the count of said second binary counting means logic means responsive to said registering means for selecting an output from said first binary counting means; means for connecting the output of said voltage controlled oscillator to an output terminal; and means for comparing phase differential between said selected output of said first binary counting means and said signal input from said variable Baud Rate Clock and generating a voltage level based upon any phase differential therebetween for adjusting said voltage controlled oscillator output frequency.
Claim 3
Dependent Claim
46 words
A digital feedback circuit as set forth in claim 1, further comprising: means for switching said system clock to said output terminal and means for outputting said system clock signal and disenabling said voltage controlled oscillator whenever said second binary means count exceeds a specified limit.
Claim 4
Dependent Claim
23 words
A digital feedback circuit as set forth in claim 1 wherein said clock generating at said preset bit frequency comprises a crystal oscillator.
Claim 5
Dependent Claim
217 words
A digital feedback circuit for synchronizing an oscillator output frequency with a signal input from a variable Baud Rate Clock in order to maintain a fixed input to output frequency ratio, comprising: first binary means connected to a voltage controlled oscillator having an output frequency voltage for counting down at a rate determined by said controlled oscillator output frequency, and having sequentially activated outputs for binary division of said output frequency; a crystal oscillator generating a system clock signal at a preset bit frequency; second binary means for counting down said system clock signal for a period determined by said Baud Rate Clock period; means registering the count of said second binary counting means logic means responsive to said registering means for selecting an output from said first binary counting means; means for connecting the output of said voltage controlled oscillator to an output terminal; means for comparing phase differential between said selected output of said first binary counting means and said signal input from said variable Baud Rate Clock and generating a voltage level based upon any phase differential therebetween for adjusting said voltage controlled oscillator output frequency; and means for switching said system clock signal to said output terminal and disenabling said voltage controlled oscillator whenever said second binary means count exceeds a specified limit.
Claim 6
Dependent Claim
217 words
A digital feedback circuit for synchronizing an oscillator output frequency with a signal input from a variable Baud Rate Clock in order to maintain a fixed input to output frequency ratio, comprising: first binary means connected to a voltage controlled oscillator having an output frequency voltage for counting down at a rate determined by said controlled oscillator output frequency, and having sequentially activated outputs for binary division of said output frequency; a crystal oscillator generating a system clock signal at a preset bit frequency; second binary means for counting down said system clock signal for a period determined by said Baud Rate Clock period; means registering the count of said second binary counting means logic means responsive to said registering means for selecting an output from said first binary counting means; means for connecting the output of said voltage controlled oscillator to an output terminal; means for comparing phase differential between said selected output of said first binary counting means and said signal input from said variable Baud Rate Clock and generating a voltage level based upon any phase differential therebetween for adjusting said voltage controlled oscillator output frequency; and means for switching said system clock signal to said output terminal and disenabling said voltage controlled oscillator whenever said second binary means count exceeds a specified limit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-11-28 | 1987-05-30 | 1987-11-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-11-28 | 1991-05-30 | 1991-11-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-11-28 | 1995-05-30 | 1995-11-29 | $7700.00 | Window Closed / Lapsed |