US4417218A
Expired / Lapsed
US
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Linearizing circuit for a high frequency voltage controlled oscillator
Assignee: United States, THR NAVY, Secretary of
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Filing: 1981-06-19
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Granted: 1983-11-22
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Expires: 2001-06-19
Abstract
Abstract A circuit for linearizing the oscillator sweep output frequency signal of a voltage controlled oscillator is disclosed. The voltage controlled oscillator is driven by the output of an op amp, which amplifies and filters the output of a D/A converter. The D/A converter responds to preselected 8-bit words, stored in an EPROM, so as to produce a desired output frequency at each memory address. The addresses, in turn, are provided by a combination of gates, counters, input signals and a clock.
Inventors
- 👤 Herbert Berke
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:37
CPC Classifications
H; H03; H03B; H03B23/00; H03B2200/00; H03B2200/006; H03B2200/0092
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
6 words
A linearizing circuit comprising, in combination:
Claim 2
Dependent Claim
6 words
A linearizing circuit comprising, in combination:
Claim 3
Dependent Claim
440 words
an input terminal adapted to receive a horizontal sync signal having a series of uniformly spaced horizontal sync pulses; timing means having an input connected to said input terminal and a plurality of outputs, for producing a plurality of digital addresses, said plurality of digital addresses to be repetitive whenever said timing means receives at the input thereof one of the sync pulses of said horizontal sync signal, said timing means comprising; a variable frequency clock having an output; a first NAND gate having a first input connected to said input terminal, a second input, and an output; a direct current voltage source having an output connected to the second input of said first NAND gate; a second NAND gate having a first input connected to the output of said first NAND gate, a second input connected to the output of said variable frequency clock, and an output; a third NAND gate having a first input connected to the output of said second NAND gate, a second input, and an output; a first counter having a clock input connected to the output of said third NAND gate, a reset input connected to the output of said first NAND gate, an enable output, and four data outputs; a second counter having a clock input connected to the output of said third NAND gate, a reset input connected to the output of said first NAND gate, an enable input connected to the enable output of said first counter, and four data outputs; a fourth NAND gate having a first input connected to the second data output of said first counter, a second input connected to the first data output of said second counter, a third input connected to the second data output of said second counter, and an output connected to the second input of said third NAND gate; memory means having a plurality of inputs effectively connected to the outputs of said timing means and plurality of outputs, for providing, in response to each digital address produced by said timing means, a digital word; means having a plurality of inputs effectively connected to the outputs of said memory means, and an output for converting each digital word provided by said memory means to an analog voltage; and voltage controlled oscillator means having an input connected to the output of said converting means and an output, for providing at the output thereof a frequency signal in response to each of said analog voltages such that a linear oscillator sweep output frequency signal is formed at the output of said voltage controlled oscillator means between successive sync pulses of said horizontal sync signal.
Claim 4
Dependent Claim
440 words
an input terminal adapted to receive a horizontal sync signal having a series of uniformly spaced horizontal sync pulses; timing means having an input connected to said input terminal and a plurality of outputs, for producing a plurality of digital addresses, said plurality of digital addresses to be repetitive whenever said timing means receives at the input thereof one of the sync pulses of said horizontal sync signal, said timing means comprising; a variable frequency clock having an output; a first NAND gate having a first input connected to said input terminal, a second input, and an output; a direct current voltage source having an output connected to the second input of said first NAND gate; a second NAND gate having a first input connected to the output of said first NAND gate, a second input connected to the output of said variable frequency clock, and an output; a third NAND gate having a first input connected to the output of said second NAND gate, a second input, and an output; a first counter having a clock input connected to the output of said third NAND gate, a reset input connected to the output of said first NAND gate, an enable output, and four data outputs; a second counter having a clock input connected to the output of said third NAND gate, a reset input connected to the output of said first NAND gate, an enable input connected to the enable output of said first counter, and four data outputs; a fourth NAND gate having a first input connected to the second data output of said first counter, a second input connected to the first data output of said second counter, a third input connected to the second data output of said second counter, and an output connected to the second input of said third NAND gate; memory means having a plurality of inputs effectively connected to the outputs of said timing means and plurality of outputs, for providing, in response to each digital address produced by said timing means, a digital word; means having a plurality of inputs effectively connected to the outputs of said memory means, and an output for converting each digital word provided by said memory means to an analog voltage; and voltage controlled oscillator means having an input connected to the output of said converting means and an output, for providing at the output thereof a frequency signal in response to each of said analog voltages such that a linear oscillator sweep output frequency signal is formed at the output of said voltage controlled oscillator means between successive sync pulses of said horizontal sync signal.
Claim 5
Dependent Claim
20 words
The circuit of claim 1 wherein the frequency of the sync pulses of said horizontal sync signal is fifteen kilohertz.
Claim 6
Dependent Claim
20 words
The circuit of claim 1 wherein the frequency of the sync pulses of said horizontal sync signal is thirty kilohertz.
Claim 7
Dependent Claim
21 words
The circuit of claim 1 wherein said digital addresses are produced by said timing means at a frequency of two megahertz.
Claim 8
Dependent Claim
19 words
The circuit of claim 1 wherein each digital address produced by said timing means comprises an eight-bit digital address.
Claim 9
Dependent Claim
16 words
The circuit of claim 1 wherein said memory means comprises an erasable programmable read only memory.
Claim 10
Dependent Claim
21 words
The circuit of claim 1 wherein each of the digital words provided by said memory means comprises an eight-bit digital word.
Claim 11
Dependent Claim
48 words
The circuit of claim 1 further characterized by: an operational amplifier connected between the output of said converting means and the input of said voltage controlled oscillator means; and the parallel combination of a resistor and a capacitor connected between the input and output of said operational amplifier.
Claim 12
Independent Claim
368 words
A system for linearizing a voltage-controlled oscillator comprising, in combination: an input terminal; a variable frequency clock having an output; a first NAND gate having a first input connected to said input terminal, a second input, and an output; a direct current voltage source having an output connected to the second input of said first NAND gate; a second NAND gate having a first input connected to the output of said first NAND gate, a second input connected to the output of said variable frequency clock, and an output; a third NAND gate having a first input connected to the output of said second NAND gate, a second input and an output; a first counter having a clock input connected to the output of said third NAND gate, a reset input connected to the output of said first NAND gate, an enable output and four data outputs; a second counter having a clock input connected to the output of said third NAND gate, a reset input connected to the output of said first NAND gate, an enable input connected to the enable output of said first counter and four data outputs; a fourth NAND gate having a first input connected to the second data output of said first counter, a second input connected to the first data output of said second counter, a third input connected to the second data output of said second counter and an output connected to the second input of said third NAND gate; an erasable programmable read only memory having eight inputs, four inputs of which are respectively connected to the four data outputs of said first counter, and four inputs of which are respectively connected to the four data outputs of said second counter, and eight outputs; a digital-to-analog converter having eight inputs respectively connected to the eight outputs of said erasable programmable read only memory, and an output; an operational amplifier having an input connected to the output of said digital-to-analog converter and an output; the parallel combination of a resistor and a capacitor connected between the input and the output of said operational amplifier; and said voltage controlled oscillator having an input connected to the output of said operational amplifier.
Claim 13
Independent Claim
368 words
A system for linearizing a voltage-controlled oscillator comprising, in combination: an input terminal; a variable frequency clock having an output; a first NAND gate having a first input connected to said input terminal, a second input, and an output; a direct current voltage source having an output connected to the second input of said first NAND gate; a second NAND gate having a first input connected to the output of said first NAND gate, a second input connected to the output of said variable frequency clock, and an output; a third NAND gate having a first input connected to the output of said second NAND gate, a second input and an output; a first counter having a clock input connected to the output of said third NAND gate, a reset input connected to the output of said first NAND gate, an enable output and four data outputs; a second counter having a clock input connected to the output of said third NAND gate, a reset input connected to the output of said first NAND gate, an enable input connected to the enable output of said first counter and four data outputs; a fourth NAND gate having a first input connected to the second data output of said first counter, a second input connected to the first data output of said second counter, a third input connected to the second data output of said second counter and an output connected to the second input of said third NAND gate; an erasable programmable read only memory having eight inputs, four inputs of which are respectively connected to the four data outputs of said first counter, and four inputs of which are respectively connected to the four data outputs of said second counter, and eight outputs; a digital-to-analog converter having eight inputs respectively connected to the eight outputs of said erasable programmable read only memory, and an output; an operational amplifier having an input connected to the output of said digital-to-analog converter and an output; the parallel combination of a resistor and a capacitor connected between the input and the output of said operational amplifier; and said voltage controlled oscillator having an input connected to the output of said operational amplifier.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-11-21 | 1987-05-23 | 1987-11-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-11-21 | 1991-05-23 | 1991-11-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-11-21 | 1995-05-23 | 1995-11-22 | $7700.00 | Window Closed / Lapsed |