Read amplifier for a bipolar memory module

Claim 2

A read amplifier for a bipolar memory module having memory cells arranged in matrix-fashion, the read amplifier evaluating a difference of higher and lower respective read currents in a first and a second bit line of the memory module, comprising: means in said read amplifier for feeding into the bit line with the higher read current an additional current generated by the read amplifier.

Claim 3

A read amplifier for a bipolar memory module having memory cells arranged in matrix-fashion, the read amplifier evaluating a difference of higher and lower respective read currents in a first and a second bit line of the memory module, comprising: means in said read amplifier for feeding into the bit line with the higher read current an additional current generated by the read amplifier; said read amplifier having means for evaluating a difference of voltage drops caused by read currents at read resistances terminating the first and second bit line, said means for evaluating comprising a differential amplifier formed of emitter-coupled transistors connected to operate with a constant current, inputs of the differential amplifier being connected via emitter followers to the bit lines; and each of the read resistances being divided up into two partial resistances, and a collector of the transistor controlled by and associated with one bit line of the differential amplifier being connected with a connection point between the partial resistances of the other bit line, and vice versa.

Claim 4

A read amplifier for a bipolar memory module having memory cells arranged in matrix-fashion, the read amplifier evaluating a difference of higher and lower respective read currents in a first and a second bit line of the memory module, comprising: means in said read amplifier for feeding into the bit line with the higher read current an additional current generated by the read amplifier; said read amplifier having means for evaluating a difference of voltage drops caused by read currents at read resistances terminating the first and second bit line, said means for evaluating comprising a differential amplifier formed of emitter-coupled transistors connected to operate with a constant current, inputs of the differential amplifier being connected via emitter followers to the bit lines; and each of the read resistances being divided up into two partial resistances, and a collector of the transistor controlled by and associated with one bit line of the differential amplifier being connected with a connection point between the partial resistances of the other bit line, and vice versa.

Claim 5

A read amplifier according to claim 2 wherein one of the partial resistances is disposed between the collector of the respective transistor of the differential amplifier and a control input of the respective emitter follower, said one partial resistance being substantially smaller than the respective other partial resistance.

Claim 6

A read amplifier according to claim 3 wherein each of said one partial resistances between the collectors of the respective transistors and the control inputs of the respective emitter followers have substantially no resistance.

Claim 7

A memory module system comprising: a bipolar memory module having a plurality of memory cells arranged in matrix-fashion and with first and second bit lines associated with the memory cells, higher and lower respective read currents occurring in the first and second bit lines during operation of the module; a read amplifier means connected to the first and second bit lines for the purpose of evaluating a difference of the higher and lower respective read currents in the first and second bit lines during operation; and means associated with the read amplifier means for feeding into the bit line with the higher read current an additional read current generated by the read amplifier means.

Claim 8

A memory module system comprising: a bipolar memory module having a plurality of memory cells arranged in matrix-fashion and with first and second bit lines associated with the memory cells, higher and lower respective read currents occurring in the first and second bit lines during operation of the module; a read amplifier means connected to the first and second bit lines for the purpose of evaluating a difference of the higher and lower respective read currents in the first and second bit lines during operation; and means associated with the read amplifier means for feeding into the bit line with the higher read current an additional read current generated by the read amplifier means.

Claim 9

A memory module system, comprising: a bipolar memory module having a plurality of memory cells arranged in matrix-fashion and with first and second bit lines associated with the memory cells, higher and lower respective read currents occurring in the first and second bit lines during operation of the module; a read amplifier means connected to the first and second bit lines for the purpose of evaluating a difference of the higher and lower respective read currents in the first and second bit lines during operation; means associated with the read amplifier means for feeding into the bit line with the higher read current an additional read current generated by the read amplifier means; the read amplifier means comprising a differential amplifier having two transistors forming two inputs and having an emitter follower connected to each input; the bit lines connecting to inputs of the respective emitter followers; a read resistance connected between the input of the respective emitter follower and a reference potential; and a collector of one of the transistors of the differential amplifier associated with one bit line connecting to the partial resistance in the other bit line between the partial resistance and the associated emitter follower, and vice-versa for a collector of the other transistor of the differential amplifier.

Claim 10

A memory module system, comprising: a bipolar memory module having a plurality of memory cells arranged in matrix-fashion and with first and second bit lines associated with the memory cells, higher and lower respective read currents occurring in the first and second bit lines during operation of the module; a read amplifier means connected to the first and second bit lines for the purpose of evaluating a difference of the higher and lower respective read currents in the first and second bit lines during operation; means associated with the read amplifier means for feeding into the bit line with the higher read current an additional read current generated by the read amplifier means; the read amplifier means comprising a differential amplifier having two transistors forming two inputs and having an emitter follower connected to each input; the bit lines connecting to inputs of the respective emitter followers; a read resistance connected between the input of the respective emitter follower and a reference potential; and a collector of one of the transistors of the differential amplifier associated with one bit line connecting to the partial resistance in the other bit line between the partial resistance and the associated emitter follower, and vice-versa for a collector of the other transistor of the differential amplifier.