Dual port memory interlock

Claim 1

A computing system comprising first (P1) processor means, second (P2) processor means, switching means (101), first bus means (DB1) connected to selectively transfer signals between said first processor means and said switching means, second bus means (DB2) connected to selectively transfer signals between said second processor means and said switching means, memory means (100) connected to receive signals from said switching means, and interlock means (103) connected to said switching means to determine which one of said first and second processor means is to be connected to said memory means via said switching means and assuring that only one processor means is so connected at any time, said interlock means operative to normally maintain a priority status for said second processor means but selectively permitting either of said signal processor means to be connected to said switching means for consecutive operations thereof at the direction of said first and second processor means, said interlock means produces a signal (P2D7) wherein said second processor means has said priority status and is normally connected to said memory means via said switching means in response to a control signal (CSZ1) from said second processor means and wherein said first processor means is connected to said memory means via said switching means only when said second processor is not so connected, said interlock means includes first and second bistable means, said first bistable means (200) connected to receive signals from said second processor means to produce signals representative of the status of said second processor means and to selectively prevent said first processor means from being connected to said switching means, said second bistable means (201) connected to receive signals from said first and second processor means and to supply signals (PNTR) to said switching means to control which of said first and second processor means is connected to said memory means as well as to supply signals (P1D7, P2D7) to said first and second processor means to indicate whether the connection of the respective processor means has been permitted, said second bistable means further connected to receive signals from said first bistable means to thereby produce signals which selectively preclude one of said first and second processor means from being connected to said memory means via said switching means, said second bistable means connected to receive an inquiry signal from said first processor means when said first processor means attempts to be connected to said memory means via said switching means and to produce an output signal in response to said inquiry signal which output signal informs said first processor means if it has obtained control.