Sampling network analyzer with sampling synchronization by means of phase-locked loop

Claim 2

An improved sampling network analyzer of the type having: (a) first sample-and-hold means for receiving a first analog signal and for producing a first sample-and-hold output signal that is a stepwise approximation to the first analog signal; (b) analog-to-digital converter means, electrically connected to the first sample and hold means, the analog-to-digital converter means for receiving the first sample and hold output signal and for producing a discrete-time digital signal that is representative of the first sample and hold output signal; (c) synchronizing means, electrically connected to the first sample-and-hold means, the synchronizing means for receiving a reference signal, characterized by a reference signal frequency, and for synchronizing, to the reference signal, operation of the first sample-and-hold means; wherein the synchronizing means comprises: (d) time-difference detector means, electrically connected to a C counter means, the time difference detector means for producing a time difference detector output signal that is related to time difference between corresponding transitions of the reference signal and a C counter output signal; (e) integrating amplifier means, electrically connected to the time difference detector means, the integrating amplifier means for receiving the time difference detector output signal and for producing a sawtooth signal that is related to an integration, with respect to time, of the time difference detector output signal; (f) third sample-and-hold means, electrically connected to the integrating amplifier means, the third sample-and-hold means for receiving the sawtooth signal and for producing a third sample-and-hold output signal that is related to the sawtooth signal; (g) voltage-controlled oscillator means, electrically connected to the third sample-and-hold means, the voltage-controlled oscillator means for receiving the third sample-and-hold output signal and for producing a VCO output signal characterized by a VCO output signal frequency that is related to the third sample-and-hold output signal; (h) Y counter means, electrically connected to the voltage-controlled oscillator means, the Y counter means for receiving the VCO output signal and for producing a Y counter output signal, the Y counter output signal characterized by a Y counter output signal frequency that is equal to the VCO output signal frequency divided by an integer factor Y; (i) C counter means, electrically connected to the Y counter means, the C counter means for receiving the Y counter output signal and for producing a C counter output signal that is characterized by a C counter output signal frequency that is equal to the Y counter output signal frequency divided by an integer factor C; wherein the Y counter output signal serves to synchronize, to the reference signal, operation of the first sample-and-hold means.

Claim 3

An improved sampling network analyzer as recited in claim 1, wherein the synchronizing means further comprises: (a) D counter means, electrically connected intermediate the reference signal and the time-difference detector means, the D counter means for receiving the reference signal, and for producing a D counter output signal characterized by a D counter output signal frequency that is equal to the reference signal frequency divided by an integer factor D, and for applying the D counter output signal to the time-difference detector means.

Claim 4

An improved sampling network analyzer as recited in claim 2, in which the integer factor D is an odd integer.

Claim 5

An improved sampling network analyzer as recited in claim 2, further comprising means for establishing the integer factor D such that an appropriate time interval is provided between successive operations of the first sample-and-hold means, the appropriate time interval being sufficient but not substantially in excess of that required for functioning of the first sample-and-hold means and the analog-to-digital converter means.

Claim 6

An improved sampling network analyzer as recited in claim 4, in which the integer factor D is an odd integer.

Claim 7

An improved sampling network analyzer as recited in claim 1, wherein the synchronizing means further comprises: (a) means, electrically connected to the C counter means and operable by an operator of the sampling network analyzer, for establishing the integer factor C in accordance with a desired number of samples per measurement.

Claim 8

An improved sampling analyzer as recited in claim 6, wherein the synchronizing means further comprises: (a) means, electrically connected to the Y counter means, for establishing the integer factor Y such that operation of the voltage-controlled oscillator means is maintained within a substantially narrow range of frequencies notwithstanding variations in the integer factor C.

Claim 9

An improved sampling network analyzer as recited in claim 1, wherein the synchronizing means further comprises: (a) means, electrically connected to the Y counter means, for establishing the integer factor Y such that operation of the voltage-controlled oscillator means is maintained within a substantially narrow range of frequencies notwithstanding substantially wide variations in the frequency of the reference signal.

Claim 10

An improved sampling network analyzer of the type having: (a) first sample-and-hold means for receiving a first analog signal and for producing a first sample-and-hold output signal that is a stepwise approximation to the first analog signal; (b) second sample-and-hold means for receiving a second analog signal and for producing a second sample-and-hold output signal that is a stepwise approximation to the second analog signal; (c) multiplexer means, electrically connected to the first sample-and-hold means and to the second sample-and-hold means, the multiplexer means for receiving the first sample-and-hold output signal and the second sample-and-hold output signal, for selecting one of such sample-and-hold output signals, and for producing a multiplexer output signal that is related to such selected sample-and-hold output signal; (d) analog-to-digital converter means, electrically connected to the multiplexer means, the analog-to-digital converter means for receiving the multiplexer output signal and for producing a discrete-time digital signal that is representative of the multiplexer output signal; (e) synchronizing means, electrically connected to the first sample-and-hold means and to the second sample-and-hold means, the synchronizing means for receiving a reference signal, characterized by a reference signal frequency, and for synchronizing, to the reference signal, operation of the first sample-and-hold means and the second sample-and-hold means; wherein the synchronizing means comprises: (f) D counter means, for receiving the reference signal and for producing a D counter output signal characterized by a D counter output signal frequency that is equal to the reference signal frequency divided by an integer factor D; (g) time difference detector means, electrically connected to the D counter means and to a C counter means, the time difference detector means for producing a time difference detector output signal that is related to time difference between corresponding transitions of the D counter output signal and a C counter output signal; (h) integrating amplifier means, electrically connected to the time difference detector means, the integrating amplifier means for receiving the time difference detector output signal and for producing a sawtooth signal that is related to an integration, with respect to time, of the time difference detector output signal; (i) third sample-and-hold means, electrically connected to the integrating amplifier means, the third sample-and-hold means for receiving the sawtooth signal and for producing a third sample-and-hold output signal that is related to the sawtooth signal; (j) voltage-controlled-oscillator means, electrically connected to the third sample-and-hold means, the voltage-controlled-oscillator means for receiving the third sample-and-hold output signal and for producing a VCO output signal characterized by a VCO output signal frequency that is related to the third sample-and-hold output signal; (k) Y counter means, electrically connected to the voltage-controlled oscillator means, the Y counter means for receiving the VCO output signal and for producing a Y counter output signal, the Y counter output signal characterized by a Y counter output signal frequency that is equal to the VCO output signal frequency divided by an integer factor Y; (l) C counter means, electrically connected to the Y counter means, the C counter means for receiving the Y counter output signal and for producing a C counter output signal that is characterized by a C counter output signal frequency that is equal to the Y counter output signal frequency divided by an integer factor C; wherein the Y counter output serves to synchronize, to the reference signal, operation of the first sample-and-hold means and the second sample-and-hold means.

Claim 11

An improved sampling network analyzer of the type having: (a) first sample-and-hold means for receiving a first analog signal and for producing a first sample-and-hold output signal that is a stepwise approximation to the first analog signal; (b) second sample-and-hold means for receiving a second analog signal and for producing a second sample-and-hold output signal that is a stepwise approximation to the second analog signal; (c) multiplexer means, electrically connected to the first sample-and-hold means and to the second sample-and-hold means, the multiplexer means for receiving the first sample-and-hold output signal and the second sample-and-hold output signal, for selecting one of such sample-and-hold output signals, and for producing a multiplexer output signal that is related to such selected sample-and-hold output signal; (d) analog-to-digital converter means, electrically connected to the multiplexer means, the analog-to-digital converter means for receiving the multiplexer output signal and for producing a discrete-time digital signal that is representative of the multiplexer output signal; (e) synchronizing means, electrically connected to the first sample-and-hold means and to the second sample-and-hold means, the synchronizing means for receiving a reference signal, characterized by a reference signal frequency, and for synchronizing, to the reference signal, operation of the first sample-and-hold means and the second sample-and-hold means; wherein the synchronizing means comprises: (f) D counter means, for receiving the reference signal and for producing a D counter output signal characterized by a D counter output signal frequency that is equal to the reference signal frequency divided by an integer factor D; (g) time difference detector means, electrically connected to the D counter means and to a C counter means, the time difference detector means for producing a time difference detector output signal that is related to time difference between corresponding transitions of the D counter output signal and a C counter output signal; (h) integrating amplifier means, electrically connected to the time difference detector means, the integrating amplifier means for receiving the time difference detector output signal and for producing a sawtooth signal that is related to an integration, with respect to time, of the time difference detector output signal; (i) third sample-and-hold means, electrically connected to the integrating amplifier means, the third sample-and-hold means for receiving the sawtooth signal and for producing a third sample-and-hold output signal that is related to the sawtooth signal; (j) voltage-controlled-oscillator means, electrically connected to the third sample-and-hold means, the voltage-controlled-oscillator means for receiving the third sample-and-hold output signal and for producing a VCO output signal characterized by a VCO output signal frequency that is related to the third sample-and-hold output signal; (k) Y counter means, electrically connected to the voltage-controlled oscillator means, the Y counter means for receiving the VCO output signal and for producing a Y counter output signal, the Y counter output signal characterized by a Y counter output signal frequency that is equal to the VCO output signal frequency divided by an integer factor Y; (l) C counter means, electrically connected to the Y counter means, the C counter means for receiving the Y counter output signal and for producing a C counter output signal that is characterized by a C counter output signal frequency that is equal to the Y counter output signal frequency divided by an integer factor C; wherein the Y counter output serves to synchronize, to the reference signal, operation of the first sample-and-hold means and the second sample-and-hold means.