US4412377A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for manufacturing a hybrid integrated circuit device
Assignee: Toshiba Corp
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Filing: 1982-01-21
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Granted: 1983-11-01
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Expires: 2002-01-21
Abstract
Abstract A method for manufacturing a hybrid integrated circuit device comprising a step of forming an Al 2 O 3 layer on a metal substrate, a step of forming on the Al 2 O 3 layer a resist layer having a pattern opposite to that of a copper layer which will be formed on the Al 2 O 3 layer by a later step, a step of forming the copper layer on the Al 2 O 3 layer using the resist layer as a mask, a step of impregnating thermosetting material into both the Al 2 O 3 layer and the copper layer, and a step of providing at least one semiconductor element on the copper layer.
Inventors
- 👤 Kenji Nagashima
- 👤 Hiroshi Matsumoto
- 👤 Masataka Tanaka
- 👤 Hirosi Oodaira
- 👤 Nobuo Iwase
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 04:36
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/22; H10; H10W; H10W40/00; H10W40/20; H10W40/25; H10W40/255; H10W70/00; H10W70/01; H10W70/05; H10W70/60; H10W70/67; H10W70/68; H10W70/6875; H10W90/00; H05K1/00; H05K1/02; H05K1/03; H05K1/05; H05K1/053; H05K2201/00; H05K2201/01; H05K2201/0104; H05K2201/0116; H05K2201/0137; H05K2201/0179; H05K2203/00; H05K2203/11; H05K2203/1147; H10W90/701; H10W90/751; H10W90/754; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/4913; Y10T29/49144
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
123 words
A method for manufacturing a hybrid integrated circuit device comprising the following steps in the stated order: a step of forming a ceramic layer on a metal substrate by flame-spraying a ceramic material onto the metal substrate; a step of forming on said ceramic layer a resist layer having a pattern opposite to that of a conductive layer which will be formed on said ceramic layer by a later step; a step of forming the conductive layer by flame-spraying a conductive material on said ceramic layer using said resist layer as a mask; a step of impregnating thermosetting insulative material into both said ceramic layer and said conductive layer; and a step of providing at least one semiconductor element on said conductive layer.
Claim 2
Independent Claim
123 words
A method for manufacturing a hybrid integrated circuit device comprising the following steps in the stated order: a step of forming a ceramic layer on a metal substrate by flame-spraying a ceramic material onto the metal substrate; a step of forming on said ceramic layer a resist layer having a pattern opposite to that of a conductive layer which will be formed on said ceramic layer by a later step; a step of forming the conductive layer by flame-spraying a conductive material on said ceramic layer using said resist layer as a mask; a step of impregnating thermosetting insulative material into both said ceramic layer and said conductive layer; and a step of providing at least one semiconductor element on said conductive layer.
Claim 3
Dependent Claim
30 words
A method for manufacturing a hybrid integrated circuit device according to claim 1 further including a step of removing the resist layer after the step of forming the conductive layer.
Claim 4
Dependent Claim
44 words
A method for manufacturing a hybrid integrated circuit device according to claim 1 wherein said ceramic material is a selected one of Al 2 O 3 , MgO.SiO 2 , 2MgO.SiO 2 , ZrO 2 .SiO 2 , MgO, BeO and TiO 2 .
Claim 5
Dependent Claim
21 words
A method for manufacturing a hybrid integrated circuit device according to claim 1 wherein said conductive material is a metal material.
Claim 6
Dependent Claim
19 words
A method for manufacturing a hybrid integrated circuit device according to claim 4 wherein said metal material is copper.
Claim 7
Dependent Claim
21 words
A method for manufacturing a hybrid integrated circuit device according to claim 2, wherein said conductive material is a metal material.
References Cited (Backward Citations)
US4031268A
Cited
US4119480A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-10-31 | 1987-05-02 | 1987-11-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-10-31 | 1991-05-02 | 1991-11-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-10-31 | 1995-05-02 | 1995-11-01 | $7700.00 | Window Closed / Lapsed |