Patent US4412237A successfully refreshed from Google Patents.
US4412237A
Expired / Lapsed
US
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Semiconductor device
Assignee: Fujitsu Ltd
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Filing: 1978-12-11
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Granted: 1983-10-25
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Expires: 1998-12-11
Abstract
Abstract Disclosed is a semiconductor device having a large number of basic cells, wherein a plurality of basic cells arranged along rows of a semiconductor substrate form a basic cell array and a plurality of the basic cell arrays are arranged along columns of the substrate, and further including spaces formed between each adjoining column. Each basic cell is comprised of first and second P-channel MIS transistors and first and second N-channel MIS transistors. The gates of both the first P-channel and the first N-channel MIS transistors form a first single common gate, and the gates of both the second P-channel and the second N-channel MIS transistors form a second single common gate. The sources or the drains of both the first P-channel and the second P-channel MIS transistors form a first single common source or drain, and the sources or the drains of both the first N-channel and the second N-channel MIS transistors form a second single common source or drain. Each of the first and second single common gates has two terminal electrodes at both sides of respective basic cell array and a central terminal electrode at the center of the respective basic cell array. Further, each of the basic cells includes a small space extending between both sides of the basic cell array, which space can be utilized as a field for distributing, along a row, interconnecting lines.
Inventors
- 👤 Nobutake Matsumura
- 👤 Ryusuke Hoshikawa
- 👤 Yoshihide Sugiura
- 👤 Hiroaki Ichikawa
- 👤 Syoji Sato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 09:57
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/903; H10D84/907; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; G11C11/413; G11C11/417; G11C11/418; G11C5/00; G11C5/06; G11C5/063; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356104; Y; Y10; Y10S; Y10S257/00; Y10S257/923
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
227 words
A semiconductor device having a large number of basic cells on a semiconductor substrate, the basic cells being arranged along rows and columns of the semiconductor substrate, characterized in that each said basic cell is comprised of a first P-channel MIS transistor, a first N-channel MIS transistor, a second P-channel MIS transistor and a second N-channel MIS transistor, wherein the gates of the first P-channel and N-channel MIS transistors are commonly connected to each other by the same electrode material, the gates of the second P-channel and N-channel MIS transistors are commonly connected to each other by the same electrode material, the sources or the drains of both the first and second P-channel MIS transistors occupy a single P-type region and are connected to each other and the sources or the drains of both the first and second N-channel MIS transistors occupy a single N-type region and are connected to each other, interconnecting lines being distributed on the semiconductor substrate, said interconnecting lines being selectively distributed adjacent the basic cells, whereby a variety of functional circuits can be obtained by suitably utilizing one or more of the basic cells, wherein in each of the basic cells, the first and second common gates are arranged in parallel to each other and, at the same time, are extended from one side to the other side of the basic cell.
Claim 2
Dependent Claim
227 words
A semiconductor device having a large number of basic cells on a semiconductor substrate, the basic cells being arranged along rows and columns of the semiconductor substrate, characterized in that each said basic cell is comprised of a first P-channel MIS transistor, a first N-channel MIS transistor, a second P-channel MIS transistor and a second N-channel MIS transistor, wherein the gates of the first P-channel and N-channel MIS transistors are commonly connected to each other by the same electrode material, the gates of the second P-channel and N-channel MIS transistors are commonly connected to each other by the same electrode material, the sources or the drains of both the first and second P-channel MIS transistors occupy a single P-type region and are connected to each other and the sources or the drains of both the first and second N-channel MIS transistors occupy a single N-type region and are connected to each other, interconnecting lines being distributed on the semiconductor substrate, said interconnecting lines being selectively distributed adjacent the basic cells, whereby a variety of functional circuits can be obtained by suitably utilizing one or more of the basic cells, wherein in each of the basic cells, the first and second common gates are arranged in parallel to each other and, at the same time, are extended from one side to the other side of the basic cell.
Claim 3
Dependent Claim
31 words
A semiconductor device as set forth in claim 1, wherein each of the gates has, at both ends, terminal electrodes and a center terminal electrode positioned between the two terminal electrodes.
Claim 4
Dependent Claim
31 words
A semiconductor device as set forth in claim 2, wherein each basic cell further includes a small space extending along a row, and the small space can contain several interconnecting lines.
Claim 5
Dependent Claim
59 words
A semiconductor device as set forth in claim 3, wherein a plurality of basic cells arranged along rows form a basic cell array, and a plurality of basic cell arrays are arranged along columns, each two adjacent basic cell arrays including a space therebetween, and the space can contain several tens of interconnecting lines, each extending along a column.
Claim 6
Dependent Claim
70 words
A semiconductor device as set forth in claim 4, wherein a first insulation layer is formed on the entire surface of the semiconductor substrate and a second insulation layer is formed on the entire top surface of the first insulation layer, and wherein the interconnecting lines extending along columns are formed on the first insulation layer, while the interconnecting lines extending along rows are formed on the second insulation layer.
Claim 7
Dependent Claim
47 words
A semiconductor device as set forth in claim 5, wherein the interconnecting lines which are located directly above the used basic cells are utilized for composing a desired functional circuit, while the areas positioned directly above the non-used basic cells are utilized for distributing the interconnecting lines.
Claim 8
Dependent Claim
45 words
A semiconductor device as set forth in claim 6, wherein at least one of the interconnecting lines extending along a column and directly above each basic cell array, is utilized as a voltage supply line to be connected to MIS transistors of the basic cells.
Claim 9
Dependent Claim
98 words
A semiconductor device as set forth in claim 7, wherein two interconnecting lines extending along a column and directly above each basic cell array, are, respectively, utilized as a first voltage supply line (V DD ) and a second voltage supply line (V SS ), the first voltage supply line being in contact with N + -regions cooperating with the first and second P-channel MIS transistors of the basic cells, respectively, and the second voltage supply line being in contact with P + -regions cooperating with the first and second N-channel MIS transistors of the basic cells, respectively.
Claim 10
Dependent Claim
29 words
A semiconductor device as set forth in claim 8, wherein both P + -region and N + -region are formed directly under said small space in each basic cell.
Claim 11
Dependent Claim
46 words
A semiconductor device as set forth in claim 6, wherein the interconnecting lines which are located in said spaces along columns and, also, the interconnecting lines which are located in said small spaces along rows, are utilized for electrically connecting the functional circuits with each other.
Claim 12
Dependent Claim
118 words
A semiconductor device as set forth in claim 11, wherein a plurality of first and second potential equalizing lines are formed above the semiconductor substrate and along rows thereof, each of the first potential equalizing lines being connected, on one hand, to a first voltage supply source and on the other hand, to each of said first voltage supply lines via through-holes, while each of the second potential equalizing lines is connected, on one hand, to a second voltage supply source and, on the other hand, to each of said second voltage supply lines via through-holes, the first and second voltage supply lines and the first and second potential equalizing lines thus forming a matrix pattern of lines.
Claim 13
Dependent Claim
20 words
A semiconductor device as set forth in claim 5, wherein the first and second gates are made of polysilicon layers.
Claim 14
Dependent Claim
21 words
A semiconductor device as set forth in claim 5, wherein the first and second gates are made of refractory metal layers.
Claim 15
Dependent Claim
26 words
A semiconductor device as set forth in claim 12, wherein first and second metal layers are formed above and along the first and second gates, respectively.
Claim 16
Dependent Claim
28 words
A semiconductor device as set forth in claim 14, wherein the first and second metal layers are connected to said terminal electrodes of respective first and second gates.
Claim 17
Dependent Claim
45 words
A semiconductor device as set forth in claim 1, wherein each basic array, provided with a plurality of basic cells arranged along rows, includes function circuits which are comprised of a single or a plurality of basic cells, the function circuits being arranged along rows.
Claim 18
Dependent Claim
49 words
A semiconductor device as set forth in claim 1, wherein basic cell arrays of a plurality of basic cells are arranged along columns, said basic cell arrays including functional circuits comprised of a single basic cell or a plurality of basic cells, said functional circuits being arranged along columns.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-10-24 | 1987-04-25 | 1987-10-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-10-24 | 1991-04-25 | 1991-10-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-10-24 | 1995-04-25 | 1995-10-25 | $7700.00 | Window Closed / Lapsed |