Patent US4410858A successfully refreshed from Google Patents.
US4410858A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electronic circuit including a current mirror circuit
Assignee: Toshiba Corp
•
Filing: 1981-06-22
•
Granted: 1983-10-18
•
Expires: 2001-06-22
Abstract
Abstract This disclosed electric circuit substantially eliminates error output which is caused by unbalanced characteristics of a pair of transistors in a current mirror circuit. An input signal is amplified by a differential amplifier. A current mirror circuit is coupled between said differential amplifier and a power supply. Switching means is coupled to said current mirror circuit for cyclically switching input and output points of said mirror circuit.
Inventors
- 👤 Hiromi Kusakabe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 11:10
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/60; H03K17/603; H03D; H03D1/00; H03D1/22; H03D1/229; H03D13/00
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
203 words
An electronic circuit having signal input and output terminals, said electronic circuit comprising: a differential amplifier having at least one input terminal and a pair of output terminals, the input terminal being coupled to said signal input terminal; a first transistor having base, emitter and collector electrodes, the collector electrode being coupled to one of said differential amplifier output terminals; a second transistor having base, emitter and collector electrodes, the collector electrode being coupled to the other of said differential amplifier output terminals, the base electrode being coupled to the base electrode of said first transistor; said emitter electrodes of said first and second transistors being coupled together to a source of potential; first switching means for connecting the base electrode of said first transistor to the collector electrode of said first transistor during a first time period, and to the collector electrode of said second transistor during a second time period; second switching means for connecting said signal output terminal to the collector electrode of said second transistor during said first time period; and to the collector electrode of said first transistor during said second time period; and, control means for cyclically controlling the switching of said first and second switching means.
Claim 2
Dependent Claim
203 words
An electronic circuit having signal input and output terminals, said electronic circuit comprising: a differential amplifier having at least one input terminal and a pair of output terminals, the input terminal being coupled to said signal input terminal; a first transistor having base, emitter and collector electrodes, the collector electrode being coupled to one of said differential amplifier output terminals; a second transistor having base, emitter and collector electrodes, the collector electrode being coupled to the other of said differential amplifier output terminals, the base electrode being coupled to the base electrode of said first transistor; said emitter electrodes of said first and second transistors being coupled together to a source of potential; first switching means for connecting the base electrode of said first transistor to the collector electrode of said first transistor during a first time period, and to the collector electrode of said second transistor during a second time period; second switching means for connecting said signal output terminal to the collector electrode of said second transistor during said first time period; and to the collector electrode of said first transistor during said second time period; and, control means for cyclically controlling the switching of said first and second switching means.
Claim 3
Dependent Claim
69 words
The electronic circuit of claim 1 further comprising: a third switching means for connecting said one output terminal of said differential amplifier to the collector electrode of said first transistor during said first time period, and to the collector electrode of said second transistor during said second time period; and said control means coupled to said third switching means for cyclically controlling the switching of said third switching means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-10-17 | 1987-04-18 | 1987-10-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-10-17 | 1991-04-18 | 1991-10-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-10-17 | 1995-04-18 | 1995-10-18 | $7700.00 | Window Closed / Lapsed |