Patent US4409259A successfully refreshed from Google Patents.
US4409259A
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MOS Dynamic RAM cell and method of fabrication
Assignee: Intel Corp
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Filing: 1982-07-29
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Granted: 1983-10-11
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Expires: 2002-07-29
Abstract
Abstract A high density CMOS dynamic RAM cell comprising a transistor and capacitance means formed in an n-well is disclosed. The capacitance means includes a polysilicon plate member disposed above a p-type region formed in the n-well. A buried contact, extending from the plate member, pierces the p-type region and contacts the well. In addition to the capacitance associated with the plate member, p-type region and well, capacitance is obtained between the side walls of the n-type regions and p-type regions.
Inventors
- 👤 Mark T. Bohr
- 👤 Kenneth K. Yu
- 👤 Ronald J. C. Chwang
- 👤 C. Neil Berglund
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 09:14
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; G11C5/00; G11C5/005; H; H10; H10B; H10B12/00; H10B12/30; H10W; H10W42/00; H10W42/20; H10W42/25
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
97 words
A process for forming a pair of storage capacitors in an n-type well for use in dynamic memory cells, comprising the steps of: forming a p-type region in said well; forming a polysilicon layer over said p-type region, said layer being doped with an n-type dopant and contacting said p-type region at a predetermined area; driving said n-type dopant from said polysilicon layer at said predetermined area through said p-type region so as to separate said p-type region into a first and a second p-type region separated by an n-type region; whereby two storage capacitors are formed.
Claim 2
Dependent Claim
97 words
A process for forming a pair of storage capacitors in an n-type well for use in dynamic memory cells, comprising the steps of: forming a p-type region in said well; forming a polysilicon layer over said p-type region, said layer being doped with an n-type dopant and contacting said p-type region at a predetermined area; driving said n-type dopant from said polysilicon layer at said predetermined area through said p-type region so as to separate said p-type region into a first and a second p-type region separated by an n-type region; whereby two storage capacitors are formed.
Claim 3
Dependent Claim
19 words
The process defined by claim 1 wherein said step of forming said p-type region comprises ion implantation with boron.
Claim 4
Dependent Claim
35 words
The process defined by claim 1 wherein said polysilicon layer is patterned to form plates over said first and second regions and wherein other areas of said layer are patterned into gate members for transistors.
Claim 5
Dependent Claim
36 words
The process defined by claim 3 including a doping step to form p-type source and drain regions for said transistors; one of said source and drain regions being formed contiguous with said first and second regions.
References Cited (Backward Citations)
US4158238A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-10-10 | 1987-04-11 | 1987-10-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-10-10 | 1991-04-11 | 1991-10-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-10-10 | 1995-04-11 | 1995-10-11 | $7700.00 | Window Closed / Lapsed |