Method of manufacturing an insulated-gate field-effect transistor

Claim 1

A method of manufacturing an insulated-gate field-effect transistor in which interdigitated source and drain fingers of one conductivity type are provided in part of an epitaxial layer of the opposite conductivity type on a more highly conductive substrate, the source fingers are short-circuited to the substrate, a gate on an insulating layer on the epitaxial layer is provided between the source and drain fingers, and a drain electrode which is interdigitated with the gate is provided to contact said drain fingers, comprising the steps of: (a) forming on said insulating layer a gate layer having a plurality of separate, mutually parallel apertures; then (b) introducing dopant determining said one conductivity type into said epitaxial layer via said apertures to form mutually parallel islands of said one conductivity type from which at least a portion of the source fingers is to be provided; then (c) providing on the epitaxial layer an etch-resistant mask having mutually-parallel apertures, each of which overlies an area of an island and is smaller than the gate layer aperture associated with the island; then (d) etching away said areas of said islands and underlying parts of the epitaxial layer to form mutually parallel grooves which extend through the epitaxial layer to said substrate, have a V-shaped cross-section, extend longitudinally along said islands and are adjoined along opposite sides by remaining parts of said islands; and then (e) providing within said apertures of the gate layer and over the walls of said grooves parallel metal fingers which extend longitudinally along said islands to short-circuit the remaining parts of said islands to the epitaxial layer and to the substrate, said remaining parts forming said source fingers of the transistor.

Claim 2

A method of manufacturing an insulated-gate field-effect transistor in which interdigitated source and drain fingers of one conductivity type are provided in part of an epitaxial layer of the opposite conductivity type on a more highly conductive substrate, the source fingers are short-circuited to the substrate, a gate on an insulating layer on the epitaxial layer is provided between the source and drain fingers, and a drain electrode which is interdigitated with the gate is provided to contact said drain fingers, comprising the steps of: (a) forming on said insulating layer a gate layer having a plurality of separate, mutually parallel apertures; then (b) introducing dopant determining said one conductivity type into said epitaxial layer via said apertures to form mutually parallel islands of said one conductivity type from which at least a portion of the source fingers is to be provided; then (c) providing on the epitaxial layer an etch-resistant mask having mutually-parallel apertures, each of which overlies an area of an island and is smaller than the gate layer aperture associated with the island; then (d) etching away said areas of said islands and underlying parts of the epitaxial layer to form mutually parallel grooves which extend through the epitaxial layer to said substrate, have a V-shaped cross-section, extend longitudinally along said islands and are adjoined along opposite sides by remaining parts of said islands; and then (e) providing within said apertures of the gate layer and over the walls of said grooves parallel metal fingers which extend longitudinally along said islands to short-circuit the remaining parts of said islands to the epitaxial layer and to the substrate, said remaining parts forming said source fingers of the transistor.