US4407589A — Error correction method and apparatus for electro…

Claim 1

Independent Claim 212 words

A method of correcting errors in an electronic digital timepiece that includes an oscillator which has a 2 n frequency output, an n stage frequency divider for reducing the oscillator output frequency to a time keeping frequency, and means for displaying the count of the time keeping frequency comprising the steps of: synchronizing the timepiece with a time standard, at the beginning of an arbitrary time period T; counting the output of the (n-m)th stage of said frequency divider during the period of time T where m is a non-negative integer less than n; obtaining a count of the output of the (n-m)th stage of said frequency divider for the period of time |E| where E is the error made by said timepiece during said time period T and is the difference between the time registered by the timepiece and the time standard at the end of the time period T; dividing the obtained count for E by the count for the period of time T and multiplying by (2 n-m +N) and then adding N to obtain a new adjustment value where N was the preceding adjustment value; and adjusting the 2 n-m divisor of the first (n-m) stages of said frequency divider by the amount of said new adjustment value.

Claim 2

Independent Claim 212 words

A method of correcting errors in an electronic digital timepiece that includes an oscillator which has a 2 n frequency output, an n stage frequency divider for reducing the oscillator output frequency to a time keeping frequency, and means for displaying the count of the time keeping frequency comprising the steps of: synchronizing the timepiece with a time standard, at the beginning of an arbitrary time period T; counting the output of the (n-m)th stage of said frequency divider during the period of time T where m is a non-negative integer less than n; obtaining a count of the output of the (n-m)th stage of said frequency divider for the period of time |E| where E is the error made by said timepiece during said time period T and is the difference between the time registered by the timepiece and the time standard at the end of the time period T; dividing the obtained count for E by the count for the period of time T and multiplying by (2 n-m +N) and then adding N to obtain a new adjustment value where N was the preceding adjustment value; and adjusting the 2 n-m divisor of the first (n-m) stages of said frequency divider by the amount of said new adjustment value.

Claim 3

Dependent Claim 44 words

A method of correcting errors in an electronic digital timepiece according to claim 1 wherein said step for obtaining a count for E includes the step of counting the output of the (n-m)th stage of said frequency divider for the period of time |E|.

Claim 4

Dependent Claim 68 words

A method of correcting errors in an electronic digital timepiece according to claim 1 wherein said step for obtaining a count for E comprises the steps of: synchronizing a time register with said time standard at the beginning of said time period T; subtracting the time in said time register from said time standard at the end of said time period T to obtain said count for E.

Claim 5

Dependent Claim 15 words

A method according to claim 1 wherein m is a positive integer less than n.

Claim 6

Dependent Claim 87 words

A method according to claim 1 wherein said step of counting the output of the (n-m)th stage of said frequency divider for a period of time |E| includes the steps of: at the end of said time period T changing the frequency of the count to the display means until the time on the display means is again synchronized with said standard time; and counting the output of the (n-m)th stage of said frequency divider during the time that the frequency to the display means is changed.

Claim 7

Dependent Claim 55 words

A method according to claim 5 wherein said step of changing the frequency of the count to the counting and display means consists of doubling the frequency of the count if the counting and display means is slow and changing the frequency of the count to zero if the counting and display means is fast.

Claim 8

Dependent Claim 235 words

In an electronic digital timepiece that includes an oscillator that has a 2 n frequency output, an n stage frequency divider for reducing the oscillator output frequency to a time keeping frequency, and means for counting and displaying the count of the time keeping frequency, apparatus for correcting errors in said timepiece due to changes in the output frequency of said oscillator comprising: a first counting means connected to the output of the (n-m)th stage of said frequency divider where m is a whole number less than n and greater than zero; a second counting means connected to the output of the (n-m)th stage of said frequency divider; means for activating said first counting means for a selected period of time T whereby the first counting means counts the output of the (n-m)th stage of said frequency divider during the period T; means for activating said second counting means for a period of time |E| where |E| is equal to the error accumulated by said time piece during said period T; means for dividing the count on said second counting means by the count on said first counting means, multiplying by (2 n-m +N) and adding N to produce a new adjustment value where N is the preceding adjustment value; and means for adjusting the 2 n-m divisor of the first (n-m)th stages of said frequency divider by the amount of said new adjustment value.

Claim 9

Dependent Claim 235 words

In an electronic digital timepiece that includes an oscillator that has a 2 n frequency output, an n stage frequency divider for reducing the oscillator output frequency to a time keeping frequency, and means for counting and displaying the count of the time keeping frequency, apparatus for correcting errors in said timepiece due to changes in the output frequency of said oscillator comprising: a first counting means connected to the output of the (n-m)th stage of said frequency divider where m is a whole number less than n and greater than zero; a second counting means connected to the output of the (n-m)th stage of said frequency divider; means for activating said first counting means for a selected period of time T whereby the first counting means counts the output of the (n-m)th stage of said frequency divider during the period T; means for activating said second counting means for a period of time |E| where |E| is equal to the error accumulated by said time piece during said period T; means for dividing the count on said second counting means by the count on said first counting means, multiplying by (2 n-m +N) and adding N to produce a new adjustment value where N is the preceding adjustment value; and means for adjusting the 2 n-m divisor of the first (n-m)th stages of said frequency divider by the amount of said new adjustment value.

Claim 10

Dependent Claim 68 words

In an electronic digital timepiece according to claim 7 wherein said means for activating said second counting means for a period of time |E| comprises: a first switching means for activating said second counting means and for increasing the time keeping frequency when E is slow; and a second switching means for activating said second counting means and for slowing the time keeping frequency when E is fast.

Claim 11

Dependent Claim 46 words

In an electronic digital timepiece according to claim 8 wherein said first and second switching means includes means for transmitting to said means for adjusting the divisor of the first (n-m)th stages of said frequency divider a signal indicative of whether E is fast or slow.

Claim 12

Dependent Claim 41 words

In an electronic digital timepiece according to claim 8 wherein said first switching means for increasing the time keeping frequency includes means for connecting the output of the (n-m)th stage of said frequency divider directly to the counting and display means.

Claim 13

Dependent Claim 33 words

In an electronic digital timepiece according to claim 8 wherein said second switch means for increasing the time keeping frequency includes means for disconnecting the frequency divider from the counting and display means.

Claim 14

Dependent Claim 15 words

In an electronic digital timepiece according to claim 8 wherein m is equal to one.

Claim 15

Dependent Claim 201 words

In an electronic digital timepiece that includes an oscillator having a 2 n frequency output, an n-stage frequency divider divider for reducing the oscillator frequency to a time keeping frequency, and a display time register counting and displaying the count of the time keeping frequency, apparatus for correcting errors in the timepiece due to changes in the output frequency of said oscillator comprising: a first register for counting the output frequency from said n-stage frequency divider for an arbitrary period of time T; a second time register for registering the time as produced by the output of said n-stage frequency divider; means for synchronizing said second time register with a time standard at the beginning of said time period T; means for obtaining the error E of the time in said second time register as compared to said time standard at the end of said time period T; computer means receiving the output of said first register means and said means for obtaining the error E for calculating a new adjustment value: N+(2.sup.n +N)E/T where N is the preceding adjustment value; and means for adjusting the 2 n divisor of the frequency divider by the amount of the new adjustment value.

Claim 16

Dependent Claim 201 words

In an electronic digital timepiece that includes an oscillator having a 2 n frequency output, an n-stage frequency divider divider for reducing the oscillator frequency to a time keeping frequency, and a display time register counting and displaying the count of the time keeping frequency, apparatus for correcting errors in the timepiece due to changes in the output frequency of said oscillator comprising: a first register for counting the output frequency from said n-stage frequency divider for an arbitrary period of time T; a second time register for registering the time as produced by the output of said n-stage frequency divider; means for synchronizing said second time register with a time standard at the beginning of said time period T; means for obtaining the error E of the time in said second time register as compared to said time standard at the end of said time period T; computer means receiving the output of said first register means and said means for obtaining the error E for calculating a new adjustment value: N+(2.sup.n +N)E/T where N is the preceding adjustment value; and means for adjusting the 2 n divisor of the frequency divider by the amount of the new adjustment value.

Claim 17

Independent Claim 190 words

A method of correcting errors in an electronic digital timepiece that includes an oscillator which has a 2 n frequency output, an n stage frequency divider for reducing the oscillator output frequency to a time keeping frequency, and means for displaying the count of the time keeping frequency comprising the steps of: synchronizing the timepiece with a time standard, at the beginning of an arbitrary time period T; counting the output of the (n-m)th stage of said frequency divider during the period of time T where m is a non-negative integer less than n; counting the output of the (n-m)th stage of said frequency divider during the period of time |E| where E is the error made by the timepiece during the period of time T; dividing the count for the period of time |E| by the count for the period of time T and multiplying by (2 n-m +N) and then adding N to obtain a new adjustment value where N was the preceding adjustment value; and adjusting the 2 n-m divisor of the first (n-m) stages of said frequency divider by the amount of said new adjustment value.

Claim 18

Independent Claim 190 words

A method of correcting errors in an electronic digital timepiece that includes an oscillator which has a 2 n frequency output, an n stage frequency divider for reducing the oscillator output frequency to a time keeping frequency, and means for displaying the count of the time keeping frequency comprising the steps of: synchronizing the timepiece with a time standard, at the beginning of an arbitrary time period T; counting the output of the (n-m)th stage of said frequency divider during the period of time T where m is a non-negative integer less than n; counting the output of the (n-m)th stage of said frequency divider during the period of time |E| where E is the error made by the timepiece during the period of time T; dividing the count for the period of time |E| by the count for the period of time T and multiplying by (2 n-m +N) and then adding N to obtain a new adjustment value where N was the preceding adjustment value; and adjusting the 2 n-m divisor of the first (n-m) stages of said frequency divider by the amount of said new adjustment value.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1986-10-03	1987-04-04	1987-10-04	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1990-10-03	1991-04-04	1991-10-04	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1994-10-03	1995-04-04	1995-10-04	$7700.00	Window Closed / Lapsed

Error correction method and apparatus for electronic timepieces

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