Method of making dense vertical FET's

Claim 1

A method of forming a dense vertical FET device including: providing a dielectrically isolated region in a substrate of monocrystalline silicon; forming a first region of opposite conductivity to the conductivity of the substrate in a surface of the dielectrically isolated region to function as one of drain and source regions of the FET; anisotropically chemical etching through the first region of opposite conductivity and into the substrate to a selected depth to produce a first recess surrounded at its upper end by the first region of opposite conductivity and having converging walls and a substantially flat bottom wall with the length of each of the converging walls in the substrate beneath the first region of opposite conductivity being the desired length of a gate channel of the FET; forming a first layer of silicon dioxide over the converging walls and the bottom wall of the first recess in the substrate; forming a second layer of a material selected from the group consisting of silicon nitride and polycrystalline silicon over the layer of silicon dioxide; forming a third layer of silicon dioxide over the second layer of material; removing each of the first layer, the second layer, and the third layer from at least a portion of the bottom wall of the first recess to expose at least the portion of the bottom wall of the first recess while leaving each of the first layer, the second layer, and the third layer on at least the converging walls of the first recess; etching an enlarged recess in the substrate through the exposed portion of the bottom wall of the first recess not protected by the first layer, the second layer, and the third layer; diffusing an impurity of opposite conductivity to the conductivity of the substrate into the walls of the enlarged recess to form a second region of opposite conductivity to the conductivity of the substrate to function as the other of the source and drain regions of the FET and a plate of a storage capacitor; removing each of the first layer, the second layer, and the third layer from the converging walls of the first recess after the second region of opposite conductivity is formed only when the second layer is silicon nitride; providing a gate oxide for the gate channel of a layer of silicon dioxide by forming a layer of silicon dioxide over the converging walls of the first recess after removal of the first layer, the second layer, and the third layer when the second layer is silicon nitride and by using the first layer of silicon dioxide when the second layer is polycrystalline silicon; and forming electrical contacts to each of the first region of opposite conductivity and the gate channel.

Claim 2

A method of forming a dense vertical FET device including: providing a dielectrically isolated region in a substrate of monocrystalline silicon; forming a first region of opposite conductivity to the conductivity of the substrate in a surface of the dielectrically isolated region to function as one of drain and source regions of the FET; anisotropically chemical etching through the first region of opposite conductivity and into the substrate to a selected depth to produce a first recess surrounded at its upper end by the first region of opposite conductivity and having converging walls and a substantially flat bottom wall with the length of each of the converging walls in the substrate beneath the first region of opposite conductivity being the desired length of a gate channel of the FET; forming a first layer of silicon dioxide over the converging walls and the bottom wall of the first recess in the substrate; forming a second layer of a material selected from the group consisting of silicon nitride and polycrystalline silicon over the layer of silicon dioxide; forming a third layer of silicon dioxide over the second layer of material; removing each of the first layer, the second layer, and the third layer from at least a portion of the bottom wall of the first recess to expose at least the portion of the bottom wall of the first recess while leaving each of the first layer, the second layer, and the third layer on at least the converging walls of the first recess; etching an enlarged recess in the substrate through the exposed portion of the bottom wall of the first recess not protected by the first layer, the second layer, and the third layer; diffusing an impurity of opposite conductivity to the conductivity of the substrate into the walls of the enlarged recess to form a second region of opposite conductivity to the conductivity of the substrate to function as the other of the source and drain regions of the FET and a plate of a storage capacitor; removing each of the first layer, the second layer, and the third layer from the converging walls of the first recess after the second region of opposite conductivity is formed only when the second layer is silicon nitride; providing a gate oxide for the gate channel of a layer of silicon dioxide by forming a layer of silicon dioxide over the converging walls of the first recess after removal of the first layer, the second layer, and the third layer when the second layer is silicon nitride and by using the first layer of silicon dioxide when the second layer is polycrystalline silicon; and forming electrical contacts to each of the first region of opposite conductivity and the gate channel.