US4406052A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Non-epitaxial static induction transistor processing
Assignee: Verizon Laboratories Inc
•
Filing: 1981-11-12
•
Granted: 1983-09-27
•
Expires: 2001-11-12
Abstract
Abstract A method for fabricating a static induction transistor starting with a high resistivity substrate on which a gate-source structure is formed. The gate-source structure is covered by a supporting layer and the wafer is etched to desired thickness. Ions are implanted in the etched surface and a drain electrode is deposited. A thick metal support layer and heat sink is electroplated on the drain electrode.
Inventors
- 👤 Adrian I. Cogan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 09:50
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D30/00; H10D30/202; Y; Y10; Y10S; Y10S438/00; Y10S438/928; Y10S438/977
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
113 words
A method for fabricating a non-epitaxial static induction transistor, said method comprising the steps of: fabricating a gate-source structure on a high resistivity silicon semiconductor wafer of one conductivity type having substantially uniform thickness; covering said gate-source structure with a thick support layer; etching the surface of said wafer opposite said support layer until the thickness of said wafer is decreased to approximately 30 microns; implanting said etched surface with ions of said one conductivity type, said implantation providing a shallow high concentration layer; depositing a metal drain electrode on said implanted surface; electroplating a thick metal layer over said metal drain electrode; and removing said thick support layer from said gate-source structure.
Claim 2
Independent Claim
113 words
A method for fabricating a non-epitaxial static induction transistor, said method comprising the steps of: fabricating a gate-source structure on a high resistivity silicon semiconductor wafer of one conductivity type having substantially uniform thickness; covering said gate-source structure with a thick support layer; etching the surface of said wafer opposite said support layer until the thickness of said wafer is decreased to approximately 30 microns; implanting said etched surface with ions of said one conductivity type, said implantation providing a shallow high concentration layer; depositing a metal drain electrode on said implanted surface; electroplating a thick metal layer over said metal drain electrode; and removing said thick support layer from said gate-source structure.
Claim 3
Dependent Claim
17 words
A method as defined in claim 1 wherein said resistivity of said wafer is approximately forty ohm-centimeters.
References Cited (Backward Citations)
US4193836A
Cited
US3828230A
Cited
US3846198A
Cited
US3930912A
Cited
US4317127A
Cited
US4230505A
Cited
US4292730A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-09-26 | 1987-03-28 | 1987-09-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-09-26 | 1991-03-28 | 1991-09-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-09-26 | 1995-03-28 | 1995-09-27 | $7700.00 | Window Closed / Lapsed |