Patent US4405980A successfully refreshed from Google Patents.
US4405980A
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Process control computer wherein data and addresses are separately processed
Assignee: Individual
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Filing: 1980-10-27
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Granted: 1983-09-20
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Expires: 2000-10-27
Abstract
Abstract A main memory of a process control computer is directly connected to a data input/output unit, and, via a separate address processor, to an address memory. A clock generator is connected to a program memory and the address memory and supplies sequential clock pulses for the execution of the program and for the simultaneous delivery of addresses in each program step. The main memory, which stores the data from the data input/output unit ater the feeding of the addresses from the address processor, supplies the data for the program step to an arithmetic logic unit, which simultaneously receives pulse-frequency driven operation commands from the program memory and feeds the operation results to the data input/output unit and/or to the main memory for storing. A program step counter connected to the program memory continues switching the program steps and controls the output of the operation commands from the program memory. The data bus of the computer is separated from the address bus thereof.
Inventors
- 👤 Bruno M. Hess
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 12:18
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/05; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/32; G06F9/322; G06F9/323; G05B2219/00; G05B2219/10; G05B2219/13; G05B2219/13083; G05B2219/15; G05B2219/15048; G05B2219/15129
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
194 words
A sequentially pulse-frequency driven process control computer, comprising a data input/output unit; an address memory; a separate address processor; an address bus; a main memory directly connected to said data input/output unit and, via said address processor and said address bus, to said address memory; a program memory; a clock generator connected to said program memory and said address memory and supplying sequential clock pulses for the execution of the program and for the simultaneous delivery of addresses in each program step; a data bus separate from said address bus; an arithmetic logic unit, said main memory storing the data from said data-output unit after the feeding of the addresses from said address processor supplying the data for the program step to said arithmetic logic unit via said data bus, said arithmetic logic unit simultaneously receiving pulse-frequency driven operation commands from said program memory and feeding the operation results via said data bus to said data input/output unit and to said main memory for storing; and a program step counter connected to said program memory and continuing switching of the program steps and controlling the output of the operation commands from said program memory.
Claim 2
Dependent Claim
194 words
A sequentially pulse-frequency driven process control computer, comprising a data input/output unit; an address memory; a separate address processor; an address bus; a main memory directly connected to said data input/output unit and, via said address processor and said address bus, to said address memory; a program memory; a clock generator connected to said program memory and said address memory and supplying sequential clock pulses for the execution of the program and for the simultaneous delivery of addresses in each program step; a data bus separate from said address bus; an arithmetic logic unit, said main memory storing the data from said data-output unit after the feeding of the addresses from said address processor supplying the data for the program step to said arithmetic logic unit via said data bus, said arithmetic logic unit simultaneously receiving pulse-frequency driven operation commands from said program memory and feeding the operation results via said data bus to said data input/output unit and to said main memory for storing; and a program step counter connected to said program memory and continuing switching of the program steps and controlling the output of the operation commands from said program memory.
Claim 3
Dependent Claim
77 words
A process control computer as claimed in claim 1, further comprising a jump register connected to said program memory and charged with program steps of a jump by said program memory, and wherein said arithmetic logic unit includes a jump instruction logic circuit connected to said program memory for receiving a jump condition from said program memory and for issuing a jump instruction to said jump register, which passes said jump instruction to said program step counter.
Claim 4
Dependent Claim
27 words
A process control computer as claimed in claim 1, wherein said arithmetic logic unit comprises a plurality of substantially constant value memories in which tables are stored.
Claim 5
Dependent Claim
29 words
A process control computer as claimed in claim 1, wherein said results from said arithmetic logic unit are directly fed to said data input/output unit as a control signal.
Claim 6
Dependent Claim
32 words
A process control computer as claimed in claim 1, further comprising a decoder, and wherein said results from said arithmetic logic unit are fed to said data input/output unit via said decoder.
Claim 7
Dependent Claim
22 words
A process control computer as claimed in claim 1, wherein said data input/output unit includes a digital/analog converter and a power amplifier.
Claim 8
Dependent Claim
18 words
A process control computer as claimed in claim 1, wherein said data input/output unit includes an analog-digital converter.
Claim 9
Dependent Claim
42 words
A process control computer as claimed in claim 1, wherein said program memory includes a control output from which a control signal is directly transmitted to peripheral units of said computer, said control signal constituting a programmable section of the program step.
Claim 10
Dependent Claim
40 words
A process control computer as claimed in claim 1, wherein said clock generator comprises an oscillator and a shift register having a first input connected to said oscillator, a second input and an output invertingly connected to said second input.
Claim 11
Dependent Claim
32 words
A process control computer as claimed in claim 1, further comprising a transfer unit connected between said data bus and said address processor for permitting access to said address processor from outside.
Claim 12
Dependent Claim
153 words
A process control computer as claimed in claim 1, wherein said arithmetic logic unit comprises arithmetic units, an input from said main memory, an intermediate memory in said input for data (A) and an intermediate memory in said input for data (B), into said main memory feeding the data (A) and (B) correspondingly called up into said intermediate memories, so that said intermediate memories keep the data static for passing them to the arithmetic units of said arithmetic logic unit, and wherein said address memory is sub-divided into three sub-memories A, B and C and said address processor consecutively calls up addresses (A), (B) and (C) in said main memory under which data (A), (B) and (C) is stored, and wherein data (A) from said main memory in said arithmetic logic unit is linked with data (B) from said main memory and the result is read into address (C) of said main memory.
Claim 13
Dependent Claim
72 words
A process control computer as claimed in claim 2, further comprising a jump cycle counter connected between said jump instruction logic circuit and said jump register for controlling the number of jump repetitions and receiving its stepping pulses from said control program, said jump cycle counter beginning, when the predetermined number of cycles has been obtained, an unconditioned jump to a program step stored at a determined location in said jump register.
Claim 14
Dependent Claim
31 words
A process control computer as claimed in claim 2, wherein said jump instruction logic circuit comprises a constant value memory in which jump conditions are stored in the form of tables.
Claim 15
Dependent Claim
35 words
A process control computer as claimed in claim 2, wherein said program memory feeds pulse-frequency driven operation commands for linkage to said arithmetic logic unit and said jump condition to said jump instruction logic circuit.
Claim 16
Dependent Claim
92 words
A process control computer as claimed in claim 3, wherein said arithmetic logic unit comprises more than three constant value memories connected in series and a first of said constant value memories executes a first linkage of data fed to said arithmetic logic unit and feeds the result to the next-succeeding one of said constant value memories for processing together with additional data and control informations fed to said arithmetic logic unit, each consecutive one of said constant value memories processing the result of the next-preceding one of said constant value memories.
Claim 17
Dependent Claim
28 words
A process control computer as claimed in claim 4, wherein said input/output unit includes an intermediate memory for providing data to be issued for output when called up.
Claim 18
Dependent Claim
41 words
A process control computer as claimed in claim 9, further comprising a plurality of exclusive OR gates having outputs constituting said clock pulse outputs, and wherein said shift register has a plurality of additional outputs connected to said exclusive OR gates.
Claim 19
Dependent Claim
15 words
A process control computer as claimed in claim 9, wherein said oscillator comprises Schmitt triggers.
Claim 20
Dependent Claim
44 words
A process control computer as claimed in claim 9, wherein said oscillator has a frequency of 10 mHz and said shift register has 40 digits so that a clock pulse period of 0.1 μs and a program step period of 4 μs are obtained.
Claim 21
Dependent Claim
33 words
A process control computer as claimed in claim 9, wherein one of the outputs of said clock pulse is connected to said program step counter for step switching to a further program step.
Claim 22
Dependent Claim
43 words
A process control computer as claimed in claim 11, wherein said arithmetic logic unit further comprises three read-only memories, two of which contain data for the linkage of data (A) and (B) and the third of which includes said jump instruction logic circuit.
Claim 23
Dependent Claim
43 words
A process control computer as claimed in claim 17, wherein said output of said shift register is invertingly connected back to said second input of said shift register and the remaining ones of said plurality of outputs of said shift register remain unused.
Claim 24
Dependent Claim
94 words
A process control computer as claimed in claim 21, wherein said arithmetic logic unit comprises a plurality of constant value memories and wherein each of data (A) and (B) are 4 bit data, of each of which only 3 bits are fed to, and processed in, a first of said constant value memories and the 4th bit of each is directly fed to a second of said constant value memories, and the result from said first constant value memory is supplied as a 4 bit information to said second of said constant value memories.
Claim 25
Dependent Claim
43 words
A process control computer as claimed in claim 23, wherein each of said first and second of said constant value memories has a 4 bit control input directly connected to said program memory and receives, pulse-frequency driven, operation commands from said program memory.
References Cited (Backward Citations)
US3729716A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-09-19 | 1987-03-21 | 1987-09-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-09-19 | 1991-03-21 | 1991-09-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-09-19 | 1995-03-21 | 1995-09-20 | $7700.00 | Window Closed / Lapsed |