US4405945A
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Synchronizing signal detector circuit
Assignee: Toshiba Corp
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Filing: 1982-02-19
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Granted: 1983-09-20
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Expires: 2002-02-19
Abstract
Abstract An AFC (auto frequency control) loop circuit is provided to generate first synchronizing pulses synchronized with horizontal synchronizing signal separated from a composite synchronizing signal. A first synchronous flip-flop connected to receive this synchronizing pulse as clock pulse and a vertical synchronizing signal separated from the composite synchronizing signal. The output of the first flip-flop is applied to an input of a second synchronous flip-flop which is connected to receive the first synchronizing pulses as clock pulses. Second synchronizing pulses are obtained by a logical product operator circuit to perform the logical product operation between an inverted output of the first flip-flop and an output of the second flip-flop. The second synchronizing pulse is produced taking the trailing edge of the vertical synchronizing signal separated from the composite synchronizing signal as a reference and thus functions as a stable vertical synchronizing signal.
Inventors
- 👤 Kenzi Sato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 15:08
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/04; H04N5/08
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
139 words
A synchronizing signal detector circuit comprising: a first synchronizing signal separator circuit for separating aifrst synchronizing signal from a composite synchronizing signal in which first and second synchronizing signals are included; a second synchronizing signal separator circuit for separating the second synchronizing signal from the composite synchronizing signal; an AFC loop for generating therein a signal synchronized in phase with the first synchronizing signal; a first synchronous flip-flop which receives, as a clock pulse, the signal generated by said AFC loop and synchronized with the first synchronizing signal, and, as an input, the second synchronizing signal; a second synchronous flip-flop which receives, as an input, the output of said first flip-flop, and operates in synchronism with the clock pulse; and a logical product operation circuit for performing a logical product operation between outputs of said first and second flip-flops.
Claim 2
Dependent Claim
139 words
A synchronizing signal detector circuit comprising: a first synchronizing signal separator circuit for separating aifrst synchronizing signal from a composite synchronizing signal in which first and second synchronizing signals are included; a second synchronizing signal separator circuit for separating the second synchronizing signal from the composite synchronizing signal; an AFC loop for generating therein a signal synchronized in phase with the first synchronizing signal; a first synchronous flip-flop which receives, as a clock pulse, the signal generated by said AFC loop and synchronized with the first synchronizing signal, and, as an input, the second synchronizing signal; a second synchronous flip-flop which receives, as an input, the output of said first flip-flop, and operates in synchronism with the clock pulse; and a logical product operation circuit for performing a logical product operation between outputs of said first and second flip-flops.
Claim 3
Dependent Claim
115 words
A synchronizing signal detector circuit comprising: a first synchronizing signal separator circuit for separating a first synchronizing signal from a composite synchronizing signal in which first and second synchronizing signals are included; a second synchronizing signal separator circuit for separating a second synchronizing signal from the composite synchronizing signal; first delay means for delaying the second synchronizing signal in accordance with a predetermined clock pulse; second delay means for delaying an output signal of said first delay means by one clock cycle responsive to the clock pulse; and means for generating a reference phase signal at the trailing edge of the second synchronizing signal in response to outputs of said first and second delay means.
Claim 4
Dependent Claim
115 words
A synchronizing signal detector circuit comprising: a first synchronizing signal separator circuit for separating a first synchronizing signal from a composite synchronizing signal in which first and second synchronizing signals are included; a second synchronizing signal separator circuit for separating a second synchronizing signal from the composite synchronizing signal; first delay means for delaying the second synchronizing signal in accordance with a predetermined clock pulse; second delay means for delaying an output signal of said first delay means by one clock cycle responsive to the clock pulse; and means for generating a reference phase signal at the trailing edge of the second synchronizing signal in response to outputs of said first and second delay means.
Claim 5
Dependent Claim
187 words
A synchronizing signal detector circuit comprising: a first synchronizing signal separator circuit for separating a first synchronizing signal from a composite synchronizing signal in which first and second synchronizing signals are included; a second synchronizing signal separator circuit for separating the second synchronizing signal from the composite synchronizing signal; an AFC loop for generating therein a signal synchronized in phase with the first synchronizing signal; frequency divider means connected to receive the second synchronizing signal as a reset releasing signal and the signal obtained by said AFC loop as a clock pulse for frequency dividing the clock pulse; a flip-flop connected to receive an output signal of said divider means as a set input and the second synchronizing signal as a reset signal; first delay means for delaying an output signal of said flip-flop in synchronism with the clock pulse; second delay means for delaying an output signal of said first delay means in synchronism with the clock pulse; and means for generating a reference phase signal at the trailing edge of the second synchronizing signal in response to outputs of said first and second delay means.
Claim 6
Dependent Claim
187 words
A synchronizing signal detector circuit comprising: a first synchronizing signal separator circuit for separating a first synchronizing signal from a composite synchronizing signal in which first and second synchronizing signals are included; a second synchronizing signal separator circuit for separating the second synchronizing signal from the composite synchronizing signal; an AFC loop for generating therein a signal synchronized in phase with the first synchronizing signal; frequency divider means connected to receive the second synchronizing signal as a reset releasing signal and the signal obtained by said AFC loop as a clock pulse for frequency dividing the clock pulse; a flip-flop connected to receive an output signal of said divider means as a set input and the second synchronizing signal as a reset signal; first delay means for delaying an output signal of said flip-flop in synchronism with the clock pulse; second delay means for delaying an output signal of said first delay means in synchronism with the clock pulse; and means for generating a reference phase signal at the trailing edge of the second synchronizing signal in response to outputs of said first and second delay means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-09-19 | 1987-03-21 | 1987-09-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-09-19 | 1991-03-21 | 1991-09-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-09-19 | 1995-03-21 | 1995-09-20 | $7700.00 | Window Closed / Lapsed |