Tone detector circuit

Claim 2

Tone detector means comprising: input means for receiving signals which may include one signal of a predetermined frequency; filter means coupled to the input means for outputting only those received signals at or near the predetermined frequency; latching means coupled to the filter means and including comparator means for determining the peak amplitude of each detected cycle, shift register means coupled to the comparator means, and logic means coupled to the shift register means outputs for providing a first output signal only in response to the reception of a first predetermined number of consecutive cycles of said signal frequency, each said cycle having at least a predetermined peak amplitude, and a second output signal only in response to the reception of a second predetermined number of consecutive cycles of said signal frequency having an absolute value less than the predetermined peak amplitude; and means coupled to the latching means and responsive to the first and second output signals.

Claim 3

Tone detector means in accordance with claim 1 wherein the received signals are broadcast signals and the input means includes at least an RF stage, circuits coupled to the RF stage for providing a signal of an intermediate frequency in response to the RF stage output and demodulator means coupled to said circuits for detecting modulation on the intermediate frequency signals.

Claim 4

Tone detector means in accordance with claim 1 wherein the signal of a predetermined frequency is a very low audio frequency and the filter means is a low-pass filter.

Claim 5

Tone detector means in accordance with claim 1 wherein the filter means is a bandpass filter centered at the predetermined frequency.

Claim 6

Tone detector means in accordance with claim 1 and wherein the comparator means includes a first comparator having a first detect threshold and coupled to receive the output of the filter means, a second comparator having a second detect threshold, the second threshold being higher than the first threshold, and coupled to receive the output of the filter means, and wherein the latching means further includes first and second latches, the first latch being coupled to be set by the first comparator output and reset by the second comparator output and wherein the shift register is coupled to be clocked by the second comparator output and has a data input coupled to the first latch, and wherein the logic means includes first and second logic gates, the second latch being coupled to be set and reset by the respective logic gate outputs.

Claim 7

Tone detector means in accordance with claim 5 and wherein the first logic gate is an AND gate and provides an output in response to the first predetermined number of consecutive 1's at the outputs of the register means, and the second logic gate is a NOR gate and provides an output in response to the second predetermined number of consecutive 0's at the outputs of the register means.

Claim 8

Tone detector means in accordance with claim 1 wherein the responsive means coupled to the latching means includes a switching circuit.

Claim 9

Tone detector means in accordance with claim 1 wherein the responsive means coupled to the latching means includes an indicator.

Claim 10

A receiver for receiving a carrier wave which is modulated with signal information proportional to M+N where M is the amplitude of an intelligence signal and N is the amplitude of an indicator signal, the receiver comprising in combination: means for selectively receiving the modulated carrier wave; means for translating the received carrier wave to one of an intermediate frequency; circuitry coupled to the translating means for providing an output signal substantially equal to M; filter means coupled to the translating means for outputting only those signals at or near the frequency of said indicator signal; latching means coupled to the filter means and including comparator means for determining the peak amplitude of each detected cycle, shift register means coupled to the comparator means, and logic means coupled to the shift register means outputs for providing a first output signal only in response to the reception of a first predetermined number of consecutive cycles of said indicator signal, each said cycle having at least a predetermined peak amplitude, and a second output signal only in response to the reception of a second predetermined number of consecutive cycles of said indicator signal having an absolute value of less than the predetermined peak amplitude; and switching means coupled to the latching means and activated in response to the first and second output signals thereof.

Claim 11

A receiver for receiving a carrier wave which is modulated with signal information proportional to M+N where M is the amplitude of an intelligence signal and N is the amplitude of an indicator signal, the receiver comprising in combination: means for selectively receiving the modulated carrier wave; means for translating the received carrier wave to one of an intermediate frequency; circuitry coupled to the translating means for providing an output signal substantially equal to M; filter means coupled to the translating means for outputting only those signals at or near the frequency of said indicator signal; latching means coupled to the filter means and including comparator means for determining the peak amplitude of each detected cycle, shift register means coupled to the comparator means, and logic means coupled to the shift register means outputs for providing a first output signal only in response to the reception of a first predetermined number of consecutive cycles of said indicator signal, each said cycle having at least a predetermined peak amplitude, and a second output signal only in response to the reception of a second predetermined number of consecutive cycles of said indicator signal having an absolute value of less than the predetermined peak amplitude; and switching means coupled to the latching means and activated in response to the first and second output signals thereof.

Claim 12

A receiver in accordance with claim 9 and wherein the indicator signal is a very low frequency signal and the filter means is a low-pass filter.

Claim 13

A receiver in accordance with claim 9 and wherein the filter means is a bandpass filter centered at the frequency of the indicator signal.

Claim 14

A receiver in accordance with claim 9 and wherein the comparator means includes a first comparator having a first detect threshold and coupled to receive the output of the filter means, a second comparator having a second detect threshold, the second threshold being higher than the first threshold, and coupled to receive the output of the filter means, and wherein the latching means further includes first and second latches, the first latch being coupled to be set by the first comparator output and reset by the second comparator output, and wherein the shift register means is coupled to be clocked by the second comparator output, and has a data input coupled to the first latch, and wherein the logic means includes first and second logic gates, the second latch being coupled to be set and reset by the respective logic gate outputs.

Claim 15

A receiver in accordance with claim 12 and wherein the first logic gate is an AND gate and provides an output in response to the first predetermined number of consecutive 1's at the outputs of the register means, and the second logic gate is a NOR gate and provides an output in response to the second predetermined number of consecutive 0's at the outputs of the register means.

Claim 16

A receiver for receiving a carrier wave which is amplitude modulated with signal information proportional to the sum of first (A) and second (B) intelligence signals and which is also modulated with signal information proportional to A-B+SP where SP is the amplitude of a stereo presence indicator signal, the receiver comprising in combination: means for selectively receiving the modulated carrier wave; means for translating the received carrier wave to one of an intermediate frequency; decoding circuitry coupled to the translating means for providing output signals which are substantially equal to the first and second intelligence signals; filter means coupled to the translating means for outputting only those signals at or very near the frequency of said stereo presence indicator signal; latching means coupled to the filter means and including comparator means for determining the peak amplitude of each detected cycle, shift register means coupled to the comparator means, and logic means coupled to the shift register means outputs for providing a first output signal only in response to the reception of a first predetermined number of consecutive cycles of said signal frequency, each said cycle having at least a predetermined peak amplitude, and a second output signal only in response to the reception of a second predetermined number of consecutive cycles of said signal frequency having an absolute value less than the predetermined peak amplitude; and switching means coupled to the latching means output and to the decoding circuitry for enabling receiver operation in stereophonic and monophonic modes in response to the first and second latching means output signals respectively.

Claim 17

A receiver for receiving a carrier wave which is amplitude modulated with signal information proportional to the sum of first (A) and second (B) intelligence signals and which is also modulated with signal information proportional to A-B+SP where SP is the amplitude of a stereo presence indicator signal, the receiver comprising in combination: means for selectively receiving the modulated carrier wave; means for translating the received carrier wave to one of an intermediate frequency; decoding circuitry coupled to the translating means for providing output signals which are substantially equal to the first and second intelligence signals; filter means coupled to the translating means for outputting only those signals at or very near the frequency of said stereo presence indicator signal; latching means coupled to the filter means and including comparator means for determining the peak amplitude of each detected cycle, shift register means coupled to the comparator means, and logic means coupled to the shift register means outputs for providing a first output signal only in response to the reception of a first predetermined number of consecutive cycles of said signal frequency, each said cycle having at least a predetermined peak amplitude, and a second output signal only in response to the reception of a second predetermined number of consecutive cycles of said signal frequency having an absolute value less than the predetermined peak amplitude; and switching means coupled to the latching means output and to the decoding circuitry for enabling receiver operation in stereophonic and monophonic modes in response to the first and second latching means output signals respectively.

Claim 18

A receiver in accordance with claim 14 and further including indicator means coupled to the latching means output for providing first and second indications in response to the first and second output signals respectively.

Claim 19

A receiver for receiving a broadcast carrier wave which is amplitude modulated with signal information proportional to the sum of first (A) and second (B) intelligence signals and which is phase modulated by an angle φ having the form φ=arc tan [C 1 (A-B+SP)/(C 2 +A+B)] where C 1 and C 2 are constants and SP is the amplitude of a stereo presence indicator signal, the receiver comprising in combination: means for selectively receiving the modulated carrier wave; means for translating the received carrier wave to one of an intermediate frequency; decoding circuitry coupled to the translating means for providing output signals which are substantially equal to the first and second intelligence signals; filter means coupled to the translating means for outputting those signals at or near the frequency of said stereo presence indicator signal; latching means coupled to the filter means and including comparator means for determining the peak amplitude of each detected cycle, shift register means coupled to the comparator means, and logic means coupled to the shift register means outputs for providing a first output signal only in response to the reception of a first predetermined number of consecutive cycles of said signal frequency, each said cycle having at least a predetermined peak amplitude, and a second output signal only in response to the reception of a second predetermined number of consecutive cycles of said signal frequency having an absolute value less than the predetermined maximum peak amplitude; and switching means coupled to the latching means output and to the decoding circuitry for enabling receiver operation in stereophonic and monophonic modes in response to the first and second latching means output signals respectively.

Claim 20

A receiver for receiving a broadcast carrier wave which is amplitude modulated with signal information proportional to the sum of first (A) and second (B) intelligence signals and which is phase modulated by an angle φ having the form φ=arc tan [C 1 (A-B+SP)/(C 2 +A+B)] where C 1 and C 2 are constants and SP is the amplitude of a stereo presence indicator signal, the receiver comprising in combination: means for selectively receiving the modulated carrier wave; means for translating the received carrier wave to one of an intermediate frequency; decoding circuitry coupled to the translating means for providing output signals which are substantially equal to the first and second intelligence signals; filter means coupled to the translating means for outputting those signals at or near the frequency of said stereo presence indicator signal; latching means coupled to the filter means and including comparator means for determining the peak amplitude of each detected cycle, shift register means coupled to the comparator means, and logic means coupled to the shift register means outputs for providing a first output signal only in response to the reception of a first predetermined number of consecutive cycles of said signal frequency, each said cycle having at least a predetermined peak amplitude, and a second output signal only in response to the reception of a second predetermined number of consecutive cycles of said signal frequency having an absolute value less than the predetermined maximum peak amplitude; and switching means coupled to the latching means output and to the decoding circuitry for enabling receiver operation in stereophonic and monophonic modes in response to the first and second latching means output signals respectively.