Two level threshold circuit

Claim 2

A threshold circuit receptive of an alternating signal and comprising in combination: means responsive to said alternating signal exceeding a first relatively lower preselected value (V L ) for producing a first output signal corresponding thereto; means responsive to said alternating signal exceeding a second relatively higher preselected value (V H ) for producing a second output signal corresponding thereto; means responsive to said first and second output signals for producing a third output signal having a first value when said alternating signal reaches value V H within time t after reaching value V L and for producing a third output signal having a second different value when said alternating signal does not reach value V H within time t after reaching value V L and means responsive to said third output signal at said second different value for producing a signal to thereafter inhibit said third output signal at said first value.

Claim 3

The combinationa as set forth in claim 1 wherein said inhibiting means is resettable upon receipt of a pulse and further including means producing said pulse to reset said inhibiting means to a non-inhibited condition subsequent to its being placed in a inhibiting condition.

Claim 4

The combination as set forth in claim 1 further including an FM-CW radar for producing a beat frequency signal being said alternating signal applied to said threshold circuit.

Claim 5

The combination as set forth in claim 1 wherein said means responsive to said alternating signal reaching value V L and value V H respectively comprises respective buffers responsive to said signal reaching said values V L and V H respectively for producing a first constant value output signal and for otherwise producing a second different constant output signal.

Claim 6

The combination as set forth in claim 4 wherein said means responsive to said first and second output signals comprises a first AND gate responsive to signals from said first buffer and second AND gate responsive to signals from said second buffer and further comprising a D type flip flop normally set to a condition such that its Q output terminal is at a logic 1 condition, said Q output terminal being coupled to respective second input terminals of said first and second AND gates and wherein the D input terminal of said flip flop is coupled to said first buffer and wherein the clock terminal of said D type flip flop is responsive to an output signal from said second AND gate delayed for time t from the receipt of the logic 1 signal from said second buffer at said second AND gate and wherein upon receipt of the logic 1 signal at the clock terminal of said flip flop, the input at said D terminal is not at a logic 1, said flip flop is reset such that its Q terminal is at a logic 0 and such that said first and second AND gates are disabled.