Patent US4403396A successfully refreshed from Google Patents.
US4403396A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device design and process
Assignee: Verizon Laboratories Inc
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Filing: 1981-12-24
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Granted: 1983-09-13
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Expires: 2001-12-24
Abstract
Abstract A method for fabricating a gate-source structure for a recessed-gate static induction transistor. Source impurities are implanted prior to forming the recessed gates. The recessed gates are formed by a first isotropic etching step and a second anisotropic etching step which results in a unique overhanging protective layer used to protect the walls of the grooves during implantation of gate impurities in the bottom of the grooves. Implantations are driven and activated to form gate and source regions, the protective layer is removed and metal deposited to form electrodes. The procedure minimizes the required number of masking steps and associated mask registration problems.
Inventors
- 👤 Richard J. Stein
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 10:59
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/012; H10D62/00; H10D62/10; H10D62/17; H10D62/343; H10P; H10P50/00; H10P50/60; H10P50/64; H10P50/642; H10P50/644; H10P50/69; H10P50/691
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
225 words
A method for forming a structure for a vertically structured semiconductor device comprising: depositing impurities on a surface of a semiconductor material of a first conductivity type to uniformly increase the impurity concentration of a contact layer adjacent said surface sufficient to provide contact areas on said surface; forming a protective layer over said surface; opening windows through said protective layer; isotropically etching grooves into said semiconductor material to form partial grooves underlying said windows to a depth through said contact layer and greater than the width of said grooves; anisotropically etching to deepen said grooves beneath said windows, the bottom of each of said grooves being at least as wide as the top thereof; depositing impurities into said semiconductor material at the bottom of said grooves to form a semiconductor region of a second conductivity type opposite said first conductivity type at the bottom of each of said grooves, the semiconductor regions at the bottom of adjacent grooves forming a channel therebetween from said contact layer to a bulk region of said semiconductor material; removing said protective layer; and depositing metal over said surface whereby said metal deposits on said contact area and on the bottom of each of said grooves, the walls of said grooves providing isolation between the metal on said contact areas and the metal on the bottoms of said grooves.
Claim 2
Independent Claim
225 words
A method for forming a structure for a vertically structured semiconductor device comprising: depositing impurities on a surface of a semiconductor material of a first conductivity type to uniformly increase the impurity concentration of a contact layer adjacent said surface sufficient to provide contact areas on said surface; forming a protective layer over said surface; opening windows through said protective layer; isotropically etching grooves into said semiconductor material to form partial grooves underlying said windows to a depth through said contact layer and greater than the width of said grooves; anisotropically etching to deepen said grooves beneath said windows, the bottom of each of said grooves being at least as wide as the top thereof; depositing impurities into said semiconductor material at the bottom of said grooves to form a semiconductor region of a second conductivity type opposite said first conductivity type at the bottom of each of said grooves, the semiconductor regions at the bottom of adjacent grooves forming a channel therebetween from said contact layer to a bulk region of said semiconductor material; removing said protective layer; and depositing metal over said surface whereby said metal deposits on said contact area and on the bottom of each of said grooves, the walls of said grooves providing isolation between the metal on said contact areas and the metal on the bottoms of said grooves.
Claim 3
Dependent Claim
28 words
A method as defined in claim 1 wherein said steps of depositing impurities are performed by the steps of implanting ions and driving and activating the implanted ions.
Claim 4
Independent Claim
128 words
A method for forming a gate-source structure for a static induction transistor, said method comprising: forming a high resistivity epitaxial semiconductor layer; depositing source impurities on a surface of said epitaxial layer; forming a protective layer over said surface; opening gate windows through said protective layer; isotropically etching said semiconductor layer to form partial gate grooves extending below said gate windows; anisotropically etching to deepen said grooves beneath said windows to a predetermined depth greater than the width thereof, the bottom of said of said gate grooves being at least as wide as the top thereof; depositing gate impurities on the bottoms of said gate grooves; removing said protective layer; and depositing metal on said source regions and said gate regions to form source and gate electrodes respectively.
Claim 5
Independent Claim
128 words
A method for forming a gate-source structure for a static induction transistor, said method comprising: forming a high resistivity epitaxial semiconductor layer; depositing source impurities on a surface of said epitaxial layer; forming a protective layer over said surface; opening gate windows through said protective layer; isotropically etching said semiconductor layer to form partial gate grooves extending below said gate windows; anisotropically etching to deepen said grooves beneath said windows to a predetermined depth greater than the width thereof, the bottom of said of said gate grooves being at least as wide as the top thereof; depositing gate impurities on the bottoms of said gate grooves; removing said protective layer; and depositing metal on said source regions and said gate regions to form source and gate electrodes respectively.
Claim 6
Dependent Claim
28 words
A method as defined in claim 3 wherein said steps of depositing impurities are performed by the steps of implanting ions and driving and activating the implanted ions.
Claim 7
Dependent Claim
26 words
A method as defined in claim 3, wherein the ratio of the depth to width of said grooves is greater than one and less than ten.
Claim 8
Dependent Claim
38 words
A method as defined in claim 5 wherein the depth of said grooves is in the range of about five to fifteen microns, the width of the semiconductor material between adjacent grooves is greater than about one micron.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-09-12 | 1987-03-14 | 1987-09-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-09-12 | 1991-03-14 | 1991-09-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-09-12 | 1995-03-14 | 1995-09-13 | $7700.00 | Window Closed / Lapsed |