Patent US4403282A successfully refreshed from Google Patents.
US4403282A
Expired / Lapsed
US
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Data processing system using a high speed data channel for providing direct memory access for block data transfers
Assignee: EMC Corp
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Filing: 1980-04-29
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Granted: 1983-09-06
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Expires: 2000-04-29
Abstract
Abstract A data processing system having a central processor unit (CPU) and a memory and further including a high speed, or "burst multiplexer", channel for permitting direct access to the memory by an input/output (I/O) device without the need to use registers and control signals from the central processor unit. The high speed channel utilizes its own memory port separate from that of the CPU and includes internal paths for transferring addresses and data between an I/O device and the memory. The channel further includes a memory allocation unit (MAP) which can be loaded by transfer of memory allocation data via substantially the same common path as the I/O data transfer. Appropriate control logic is also included to control the data and address transfers and the MAP load and dump operations so that blocks of data words can be transferred sequentially and directly to or from the memory.
Inventors
- 👤 Kenneth D. Holberger
- 👤 Joseph E. Samson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 15:53
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F12/00; G06F12/02; G06F12/0223; G06F12/0292; G06F13/00; G06F13/10; G06F13/14; G06F13/20; G06F13/28; G06F12/08; G06F12/10; G06F12/1081
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
276 words
A data processing system comprising a central processor unit and a memory, said system further including channel means separate from said central processor unit for permitting direct access to said memory by input/output devices external to said central processor unit, said channel means including memory allocation means capable of translating logical addresses from a selected input/output device into physical addresses for said memory in response to a request therefor from said selected input/output device; data transfer means for providing a direct transfer of a block of one or more data words directly between a selected input/output device and said memory upon request from said input/output device and for providing a direct transfer of memory allocation information between said memory allocation means and said memory upon request from said central processor unit; address transfer means capable of transferring to said memory physical addresses which have been translated from logical addresses received from said selected input/output device and further capable of transferring to said memory physical addresses which have been received from said selected input/output device; and control means being responsive to a request signal from a selected input/output device for a transfer of a block of one or more data words and being further responsive substantially at the time of said request to an input signal from said input/output device identifying the direction of transfer of said block of data words and to another input signal identifying whether said transfer requires a memory address translation by said memory allocation means, said control means supplying control signals to said address transfer means, to said data transfer means, and to said memory allocation means for controlling the operations thereof.
Claim 2
Dependent Claim
276 words
A data processing system comprising a central processor unit and a memory, said system further including channel means separate from said central processor unit for permitting direct access to said memory by input/output devices external to said central processor unit, said channel means including memory allocation means capable of translating logical addresses from a selected input/output device into physical addresses for said memory in response to a request therefor from said selected input/output device; data transfer means for providing a direct transfer of a block of one or more data words directly between a selected input/output device and said memory upon request from said input/output device and for providing a direct transfer of memory allocation information between said memory allocation means and said memory upon request from said central processor unit; address transfer means capable of transferring to said memory physical addresses which have been translated from logical addresses received from said selected input/output device and further capable of transferring to said memory physical addresses which have been received from said selected input/output device; and control means being responsive to a request signal from a selected input/output device for a transfer of a block of one or more data words and being further responsive substantially at the time of said request to an input signal from said input/output device identifying the direction of transfer of said block of data words and to another input signal identifying whether said transfer requires a memory address translation by said memory allocation means, said control means supplying control signals to said address transfer means, to said data transfer means, and to said memory allocation means for controlling the operations thereof.
Claim 3
Dependent Claim
82 words
A data processing system in accordance with claim 1 wherein said address transfer means includes means, responsive during a transfer of a block of data words to information identifying the number of data word addresses in a block thereof to be transferred, for counting the number of data word addresses as the data words are sequentially transferred between said input/output devices and said memory and for providing a signal indicating when the last data word in a block has been so transferred.
Claim 4
Dependent Claim
51 words
A data processing system in accordance with claim 2 wherein said data transfer means includes parity check means responsive to said data words which are being transferred for determining whether a data word error has occurred and for halting the transfer of said data words until said error has been corrected.
Claim 5
Dependent Claim
49 words
A data processing system in accordance with claim 3 wherein said address transfer means includes parity check means responsive to physical addresses which are being transferred for determining whether an address error has occurred and for halting the transfer of data words until said address error has been corrected.
Claim 6
Dependent Claim
34 words
A data processing system in accordance with claim 1, said data transfer means including common data transfer paths internal to said channel means capable of transferring said data words and said memory allocation information.
Claim 7
Dependent Claim
59 words
A data processing system in accordance with claim 5 and further including multiplexer means connected in said common data transfer paths for providing the multiplexed transfer of said data words and said memory allocation information between said channel means and said memory depending on whether a transfer of data words or a transfer of memory allocation information is required.
Claim 8
Dependent Claim
87 words
A data processing system in accordance with claim 1 wherein said address transfer means includes address register means which, during the transfer of memory allocation information into said memory allocation means, is responsive to first addresses identifying the locations in said memory of said memory allocation information for supplying said first addresses to said memory and responsive to second addresses identifying the locations in said memory allocation means where the memory allocation information is to be located for supplying said second addresses to said memory allocation means.
Claim 9
Dependent Claim
35 words
A data processing system in accordance with claim 7 wherein said address transfer means further includes multiplexer means for providing for the multiplexed transfer of said first and second addresses into said address register means.
Claim 10
Dependent Claim
72 words
A data processing system in accordance with claim 2 wherein said address counting means is responsive, during a transfer of memory allocation information, to information identifying the number of memory allocation information addresses to be transferred for counting the number of memory allocation information addresses as said memory allocation information is transferred and for providing a signal indicating when said memory allocation information has been completely transferred to said memory allocation means.
Claim 11
Dependent Claim
93 words
A data processing system in accordance with claim 1 wherein the addresses received from a selected input/output device include page address information and word address information and said address transfer means includes a first transfer path for transferring the word address information directly to said memory and a second transfer path for selectively permitting the page address information to be transferred directly to said memory without translation or to be transferred to said memory allocation means for translation of said page address into a physical page address for subsequent transfer to said memory.
Claim 12
Dependent Claim
79 words
A data processing system in accordance with claim 1 wherein said control means includes means for providing a ready signal to said selected input/output device for indicating when said channel means is ready for a transfer of a block of data words; and means for providing a data signal to said selected input/output device after said ready signal has been provided and when said data word transfer is occurring for permitting said block of data words to be transferred.
Claim 13
Dependent Claim
49 words
A data processing system in accordance with claim 1, wherein said control means further includes means responsive to a parity enabling signal from said input/output device for enabling the detection of errors in the addresses received from said input/output device and in the data words which are being transferred.
Claim 14
Dependent Claim
63 words
A data processing system in accordance with claim 1 wherein said memory allocation means includes a plurality of allocation regions, the number of logical address entries in each said region being substantially equal to the entire logical address base of said system, each input/output device being capable of selecting any one of said allocation regions for use in a logical address translation operation.
Claim 15
Dependent Claim
217 words
A channel bus means for use in a data processing system having a central processor unit, a memory, a channel means separate from the central processor unit for providing direct access to the memory by one or more units external to the central processor unit, said one or more external units having interface means, and channel control means for controlling the operation of said channel means, said channel bus means providing a bus interface between said channel control means and the interface means of said one or more external units and including means responsive to a request signal from an external unit interface means requesting a data transfer between an external unit and said memory for supplying said request signal to said channel control means; means responsive to a direction signal from said external interface means indicating the direction of said data transfer for supplying said direction signal to said channel control means; means responsive to a ready signal from said channel control means indicating said channel means is ready for said data transfer to occur for supplying said ready signal to said external unit interface means; and means responsive to a data signal from said channel control means indicating that said data transfer is occurring for supplying said data signal to said external unit interface means.
Claim 16
Dependent Claim
217 words
A channel bus means for use in a data processing system having a central processor unit, a memory, a channel means separate from the central processor unit for providing direct access to the memory by one or more units external to the central processor unit, said one or more external units having interface means, and channel control means for controlling the operation of said channel means, said channel bus means providing a bus interface between said channel control means and the interface means of said one or more external units and including means responsive to a request signal from an external unit interface means requesting a data transfer between an external unit and said memory for supplying said request signal to said channel control means; means responsive to a direction signal from said external interface means indicating the direction of said data transfer for supplying said direction signal to said channel control means; means responsive to a ready signal from said channel control means indicating said channel means is ready for said data transfer to occur for supplying said ready signal to said external unit interface means; and means responsive to a data signal from said channel control means indicating that said data transfer is occurring for supplying said data signal to said external unit interface means.
Claim 17
Dependent Claim
52 words
A channel bus means in accordance with claim 14 wherein said channel bus means further includes means responsive to a parity enabling signal from said external unit interface means enabling the detection of errors in addresses received from said external unit for supplying said parity enabling signal to said channel control means.
Claim 18
Dependent Claim
52 words
A channel bus means in accordance with claim 14 or 15 wherein said channel bus means further includes means responsive to an address translation signal from said external unit interface means indicating whether said data transfer requires a memory address translation for supplying said address translation signal to said channel control means.
Claim 19
Dependent Claim
59 words
A channel bus means in accordance with claim 16 wherein said channel bus means further includes means responsive to a word count signal from said external unit interface means indicating the number of data words to be transferred when a block of data words is to be transferred for supplying said word count signal to said channel control means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-09-05 | 1987-03-07 | 1987-09-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-09-05 | 1991-03-07 | 1991-09-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-09-05 | 1995-03-07 | 1995-09-06 | $7700.00 | Window Closed / Lapsed |