Patent US4402127A successfully refreshed from Google Patents.
US4402127A
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Method of manufacturing a logic circuit including at least one field-effect transistor structure of the normally-off type and at least one saturable resistor
Assignee: Thales SA
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Filing: 1981-08-21
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Granted: 1983-09-06
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Expires: 2001-08-21
Abstract
Abstract A method of manufacturing a logic circuit having at least one field effect transistor connected in series with at least one saturable resistor, wherein an active semiconductor layer is formed with a predetermined thickness on a semi-insulating substrate, ohmic contacts are deposited to produce source and drain regions for the resistor and the transistor, a Schottky contact is deposited between the resistor source and drain ohmic contacts to form a gate region which is then electrically connected to the resistor source contact by means of a metal connection, whereupon the localized thickness of the active layer is measured by measuring the drain-source current to the resistor upon application of a predetermined voltage thereto and a groove then cut between the source and drain contacts of the field effect transistor to obtain a predetermined channel depth from the bottom of the groove to the semi-insulating substrate. Then, a Schottky contact is deposited in the groove of the field effect transistor and the logic circuit completed conventionally.
Inventors
- 👤 Ngu T. Pham
- 👤 Gerard Nuzillat
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 14:40
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0952; H10; H10N; H10N80/00; H10N89/00
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
247 words
A method of manufacturing a logic circuit having at least one field effect transistor and at least one saturable resistor, comprising: forming an active semiconductor layer on a face of a semi-insulating substrate, said active layer formed with a thickness of at least a predetermined value a 1 ; depositing simultaneously ohmic contacts to produce source and drain regions for said at least one saturable resistor and said at least one field effect transistor; depositing a Schottky contact between the source and drain ohmic contacts of said at least one saturable resistor to form a gate region; depositing a metal connection between the source contact and the Schottky contact of said at least one saturable resistor; applying a voltage to the source and drain contact of said at least one saturable resistor and then measuring the drain-source current therein to deduce therefrom a measure of the localized thickness of a 1 at the location of the logic circuit including the at least one saturable resistor and the at least one field effect transistor; cutting a groove between the source and drain contacts of the at least one field effect transistor to obtain a predetermined channel depth a o from the bottom of said groove to said semi-insulating substrate, the depth of said groove (a 1 -a o ) being determined by the localized measurement of a 1 from the preceding step; and depositing a Schottky contact in the groove of said at least one field effect transistor.
Claim 2
Independent Claim
247 words
A method of manufacturing a logic circuit having at least one field effect transistor and at least one saturable resistor, comprising: forming an active semiconductor layer on a face of a semi-insulating substrate, said active layer formed with a thickness of at least a predetermined value a 1 ; depositing simultaneously ohmic contacts to produce source and drain regions for said at least one saturable resistor and said at least one field effect transistor; depositing a Schottky contact between the source and drain ohmic contacts of said at least one saturable resistor to form a gate region; depositing a metal connection between the source contact and the Schottky contact of said at least one saturable resistor; applying a voltage to the source and drain contact of said at least one saturable resistor and then measuring the drain-source current therein to deduce therefrom a measure of the localized thickness of a 1 at the location of the logic circuit including the at least one saturable resistor and the at least one field effect transistor; cutting a groove between the source and drain contacts of the at least one field effect transistor to obtain a predetermined channel depth a o from the bottom of said groove to said semi-insulating substrate, the depth of said groove (a 1 -a o ) being determined by the localized measurement of a 1 from the preceding step; and depositing a Schottky contact in the groove of said at least one field effect transistor.
Claim 3
Dependent Claim
37 words
A method according to claim 1, wherein said form step comprises: controlling the thickness a 1 of said active semiconductor layer by measuring the doping concentration thereof as a function of the depth in said active layer.
Claim 4
Dependent Claim
45 words
A method according to claim 2, wherein said controlling step comprises: measuring the capacitance of said active semiconductor layer in relation to the growth of the depth of a depleted region in said active layer in dependence upon application of a growing d.c. voltage thereto.
Claim 5
Dependent Claim
46 words
A method according to claim 1, for manufacturing a logic circuit having plural stages, each stage comprising at least one of said field effect transistors connected in series with at least one of said saturable resistors, comprising: insulating each of said stages after said forming step.
Claim 6
Dependent Claim
34 words
A method according to claim 1, further comprising: forming dielectric deposits at the location of predetermined connection crossings of said logic circuit after deducing the localized thickness a 1 prior to cutting said groove.
Claim 7
Dependent Claim
31 words
A method according to claim 1, further comprising: forming dielectric deposits at the location of predetermined connection crossings of said logic circuit after depositing said Schottky contact in the cut groove.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-09-05 | 1987-03-07 | 1987-09-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-09-05 | 1991-03-07 | 1991-09-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-09-05 | 1995-03-07 | 1995-09-06 | $7700.00 | Window Closed / Lapsed |