Circuit arrangement for discharging a capacity

Claim 2

A semiconductor device comprising a semiconductor body having a switching device for transferring a quantity of charge Q s from a first capacitor C s to a second capacitor Cd within a time interval T having a definite duration, characterized in that means are provided for periodically transferring during said time interval a fixed quantity of charge Q t back to C s at a frequency n/T, where n and Q t are chosen so that for a period of t<T, where t is measured from charge transport, charge transferred from C s per unit of time is approximately equal to charge transferred back into C s in the same unit of time, and the potential of C s is substantially independent of Q s .

Claim 3

A semiconductor device as claimed in claim 1, characterized in that Q t is at most approximately 0.1 of the maximum value of Q s .

Claim 4

A semiconductor device as claimed in claim 1, characterized in that a number of elements are present in which information in the form of electronic charge can be generated and/or stored and that furthermore selection means are present for selectively coupling said elements to the electrode of C s , connected to said switching device, for transferring information stored in said elements to C s .

Claim 5

A semiconductor device as claimed in claim 1, characterized in that said switching device is of a field effect type and comprises two surface regions which adjoin a surface of said semiconductor body and which form a source and drain region of the field effect device said source and drain region being coupled to said first and second capacitor, respectively, and said source and drain region being separated from each other by a channel region, said channel region when viewed in the direction of current passage from source region to drain region comprising at least two gate electrodes situated one behind the other with said first gate electrode being destined to control current passage through said channel region and said second gate electrode being destined to induce in the underlying part of the channel region a potential well to store the charge Q t which can be transferred back to the source region by applying a suitable voltage to said second gate electrode.

Claim 6

A semiconductor device as claimed in claim 4, characterized in that means are present for obtaining upon applying a voltage to the second gate electrode an asymmetric potential profile with a potential well near the edge of said second gate electrode situated on the side of the source region in the part of the semiconductor body below said second gate electrode.

Claim 7

A semiconductor device as claimed in claim 5, characterized in that said means for obtaining an asymmetric potential profile comprise a region situated at the area of said potential well and having a doping concentration differing from that of adjoining surface parts of said semiconductor body.

Claim 8

A semiconductor device as claimed in claim 6, characterized in that said region at the area of said potential well below said second gate electrode is formed by a zone implanted with impurities.

Claim 9

A semiconductor device as claimed in claim 4, characterized in that means are provided for filling said potential well below said second gate electrode, after transferring back the charge Q t to the source region, with charge before fresh charge is transferred from said source region to said drain region.

Claim 10

A semiconductor device as claimed in claim 8, characterized in that said means for filling the potential well below said second gate electrode comprise a third gate electrode between said second gate electrode and said drain region for inducing a second potential well in the underlying part of said semiconductor body in which well charge can be stored at least at the value of Q t .

Claim 11

A semiconductor device as claimed in claim 9, characterized in that means are provided upon applying a voltage to the third gate electrode in the underlying part of the semiconductor body for forming an asymmetric potential profile with a potential well below and near the edge of said third gate electrode situated on the side of said source region.

Claim 12

A semiconductor device as claimed in claim 10, characterized in that said means for forming an asymmetric potential profile comprise a surface region situated at the area of the potential well to be formed and having a doping concentration differing from that of adjoining parts of said semiconductor body.

Claim 13

A picture pick-up camera comprising a semiconductor device as claimed in claim 11.

Claim 14

A semiconductor device as claimed in claim 3, characterized in that said electrode of C s comprises a strip-shaped conductor forming, together with the associated information-containing elements, part of a picture pick-up device comprising a number of similar strip-shaped conductors and associated information elements, said information elements being formed by a mosaic of photosensitive cells arranged in lines and columns.

Claim 15

A semiconductor device as claimed in claim 13, characterized in that said strip-shaped conductors extend parallel to the column direction of the mosaic and are each individually connected to an associated switching device.

Claim 16

A semiconductor device as claimed in claim 14, characterized in that said switching devices, which are connected on one side to the strip-shaped conductors, are connected on the other side to parallel inputs of a charge transfer register wherein signal charges Q s can be transferred parallel per line via the switching devices in said charge transfer register, and wherein said signal charges Q s can be transported to an output so as to be derived elsewhere in series.

Claim 17

A semiconductor device as claimed in claim 13, characterized in that said parameter n and Q t are chosen so that t is smaller than or equal to the line flyback time.

Claim 18

A picture pick-up camera comprising a semiconductor device as claimed in claim 13.