Phase tolerant bit synchronizer for digital signals

Claim 2

Apparatus for generating a clock signal synchronous with the bit rate of a received data signal comprising: voltage controlled oscillator means, said oscillator means generating a first clock signal whose frequency varies as a function of a net control voltage applied thereto; means for generating a second clock signal shifted by 180° from said first clock signal; means responsive to said first and second clock signals and said received data signal, for respectively outputting first and second signals representative of said received data signal, said second signal being shifted by an amount proportional to the phase difference between said second clock signal and said received data signal, and said first signal being shifted by one-half bit period from said second signal; means responsive to said received data signal and said first data representative signal, for producing a first output signal having a variable width proportional to the phase difference between said received data signal and said first clock signal; means responsive to said second data representative signal and the complement of said first data representative signal, for producing a second output signal having a fixed width of one-half bit period; and means for summing said output signals to generate a net control voltage which is applied to said oscillator means, whereby the frequency and phase of said first clock signal is synchronized with that of said received data signal.

Claim 3

The apparatus of claim 1 wherein said second clock generating means is an inverter responsive to said first clock signal.

Claim 4

The apparatus of claim 1 further including filter means connected between said summing means and said oscillator means, said filter means including means for maintaining phase lock between said first clock signal and said received data signal in the absence of received data transitions in said data signal.

Claim 5

The apparatus of claim 1 further including means for squaring said received data signals prior to their application to said data representative signal outputting means.

Claim 6

The apparatus of claim 1 wherein said means for outputting first and second data representative signals comprise a pair of clocked register means, each register means having an input for receiving said received data signals, one of said register means being clocked by said first clock signal and the other of said register means being clocked by said second clock signal.

Claim 7

The apparatus of claim 5 wherein said register means comprise first and second D-type flip-flops, said flip-flops having their respective D inputs connected to said received data signal, said first flip-flop having its clock input connected to said first clock signal and its Q output connected to an input of said variable width output signal producing means and its Q output connected to an input of said fixed width output signal producing means, said second flip-flop having its clock input connected to said second clock signal and its Q output connected to an input of said fixed width output signal producing means.

Claim 8

The apparatus of either claim 1 or 6 wherein said fixed and variable width output signal generating means each comprise exclusive-OR gates.

Claim 9

Apparatus for generating a clock signal synchronous with the bit rate of a received data signal comprising: phase-looked loop means including a loop filter, a loop amplifier, and a voltage controlled oscillator, said oscillator generating a first clock signal whose frequency varies as a function of a net control voltage applied thereto; means for generating a second clock signal shifted by 180° from said first clock signal; first and second register means, each having inputs responsive to said received data signal and inputs responsive respectively to said first and second clock signals, each register outputting first and second signals representative of said received data signal and the logical complement of said received data signal, the output signals of said second register means being shifted by one-half bit period from the output signals of said first register means; first and second phase error detecting means, said first phase error detecting means having an input responsive to said first output signal of said second register means and to said complementary signal output of said first register means whereby said first phase error detecting means produces an output signal having a fixed width of one-half bit period, said second phase error detecting means having an input responsive to said received data signal and to said first signal output of said first register means, whereby said second phase error detecting means produces an output signal complementary to said fixed width output signal and having a width proportional to the phase difference between said received data signal and said first clock signal; and means for summing said output signals of said phase error detecting means to generate a net control voltage which is applied to said phase-looked loop means, whereby the frequency and phase of said first clock signal is synchronized with that of said received data signal.

Claim 10

Apparatus for generating a clock signal synchronous with the bit rate of a received data signal comprising: phase-looked loop means including a loop filter, a loop amplifier, and a voltage controlled oscillator, said oscillator generating a first clock signal whose frequency varies as a function of a net control voltage applied thereto; means for generating a second clock signal shifted by 180° from said first clock signal; first and second register means, each having inputs responsive to said received data signal and inputs responsive respectively to said first and second clock signals, each register outputting first and second signals representative of said received data signal and the logical complement of said received data signal, the output signals of said second register means being shifted by one-half bit period from the output signals of said first register means; first and second phase error detecting means, said first phase error detecting means having an input responsive to said first output signal of said second register means and to said complementary signal output of said first register means whereby said first phase error detecting means produces an output signal having a fixed width of one-half bit period, said second phase error detecting means having an input responsive to said received data signal and to said first signal output of said first register means, whereby said second phase error detecting means produces an output signal complementary to said fixed width output signal and having a width proportional to the phase difference between said received data signal and said first clock signal; and means for summing said output signals of said phase error detecting means to generate a net control voltage which is applied to said phase-looked loop means, whereby the frequency and phase of said first clock signal is synchronized with that of said received data signal.

Claim 11

The apparatus of claim 8 wherein said second clock generating means is an inverter responsive to said first clock signal.

Claim 12

The apparatus of claim 8 further including means for squaring said received data signals prior to their application to said register means.

Claim 13

The apparatus of claim 8 wherein said register means each comprise D-type flip-flops each having D and clock inputs and wherein said first and second outputs respectively are Q and Q outputs.

Claim 14

The apparatus of either claim 8 or 11 wherein each said phase error detecting means comprise logic means for performing an exclusive-OR function.

Claim 15

The apparatus of claim 8 wherein said received data signal is an NRZ encoded signal and said first clock signal is generated at the bit rate of said received data signal.

Claim 16

The apparatus of claim 8 wherein said received data signal is a biphase, delay-modulation, or delay-modulation squared encoded signal and said first clock signal is generated at twice the bit rate of said received data signal.

Claim 17

The apparatus of claim 8 further including means for maintaining phase-lock in said phase-locked loop in the absence of data transitions in said received data signal.

Claim 18

The apparatus of claim 15 wherein said loop filter comprises an R-C filter containing a resistor and a capacitor connected in series, said resistor being connected to an input to said loop amplifier and said capacitor being connected to groun said loop amplifier containing an output which is connected to an input to said oscillator, and wherein said phase-lock maintaining means comprises a pair of diodes and a resistance all connected in parallel to the output of said summing means, said diodes having their polarities reversed with respect to each other and said resistance being of a value substantially greater than the resistance of said R-C filter such that the center frequency of said loop filter is maintained at the previous received data signal bit rate in the absence of output signals from said phase error detecting means, whereby said first clock signal is generated at a rate synchronized to the average value of the bit rate of the previously received data signal.