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US4400666A
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Fixed rate delay circuit
Assignee: Japan Broadcasting Corp
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Filing: 1981-01-23
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Granted: 1983-08-23
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Expires: 2001-01-23
Abstract
Abstract A binary number 2 n can be divided at a rate 2 m by means of shifting down successive digits thereof by m digits, n and m being positive integers which have a relation n>m therebetween. According to the above principle, successive digits of a binary number, which represents the number of clock pulses corresponding to an immediately preceding pulse interval of a pulse sequence having pulse intervals varied every moment, are shifted down by m digits. Thereafter, the coincidence between those shifted down successive digits and successive digits of a binary number which represents the number of clock pulses corresponding to a required fixed rate delay time is detected through plural exclusive OR gates, so as to find an instant to which the pulse sequence should be dalayed. As a result, the fixed rate delaying of the pulse sequence can be effected at the rate 1/2 m of the immediately preceding pulse interval. This fixed rate delaying of the pulse sequence is particularly fit for the clock pulse reproduction in a digital VTR or a PCM recorder operating at varied speeds. The above fixed rate delaying of the pulse sequence can be efficiently employed for a digital frequency multiplier and a digital frequency differential discriminator.
Inventors
- 👤 Takuji Sekiguchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 21:54
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/135; G; G06; G06F; G06F7/00; G06F7/60; G06F7/68; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B20/1407; G11B20/1419
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
270 words
A fixed rate delay circuit, wherein an input pulse sequence having time varied pulse intervals is delayed sequentially at a fixed rate of one divided by an integer'th power of 2 of an immediately preceding pulse interval in order, comprising a binary counter for counting clock-pulses having a predetermined repetition interval every time prior to a reset signal applied thereto, a latch circuit for latching respectively every digit of a binary number of the clock-pulses counted by said binary counter in response to the input of a latch signal just preceding said reset signal, a timing pulse generator for generating said latch signal which consists of differential pulses corresponding respectively to each pulse of said input pulse sequence and for forming said reset signal by delaying said differential pulse by a time duration being shorter than the repetition interval of said clock-pulses, a plurality of exclusive OR gates, to respective first inputs of which every digit of said binary number of the clock-pulses counted by said binary counter is applied in order and to respective second inputs of which every digit of said binary number which is latched by said latch circuit is applied in order after being shifted down respectively by integral digits for deriving respective OR output signals when said every digit applied to the respective first inputs and every shifted down digit applied to the respective second inputs coincide with each other in order, and a NOR gate, to which the respective OR output signals of said plurality of exclusive OR gates are applied, for deriving said input pulse sequence after being delayed at said fixed rate.
Claim 2
Dependent Claim
270 words
A fixed rate delay circuit, wherein an input pulse sequence having time varied pulse intervals is delayed sequentially at a fixed rate of one divided by an integer'th power of 2 of an immediately preceding pulse interval in order, comprising a binary counter for counting clock-pulses having a predetermined repetition interval every time prior to a reset signal applied thereto, a latch circuit for latching respectively every digit of a binary number of the clock-pulses counted by said binary counter in response to the input of a latch signal just preceding said reset signal, a timing pulse generator for generating said latch signal which consists of differential pulses corresponding respectively to each pulse of said input pulse sequence and for forming said reset signal by delaying said differential pulse by a time duration being shorter than the repetition interval of said clock-pulses, a plurality of exclusive OR gates, to respective first inputs of which every digit of said binary number of the clock-pulses counted by said binary counter is applied in order and to respective second inputs of which every digit of said binary number which is latched by said latch circuit is applied in order after being shifted down respectively by integral digits for deriving respective OR output signals when said every digit applied to the respective first inputs and every shifted down digit applied to the respective second inputs coincide with each other in order, and a NOR gate, to which the respective OR output signals of said plurality of exclusive OR gates are applied, for deriving said input pulse sequence after being delayed at said fixed rate.
Claim 3
Dependent Claim
92 words
A fixed rate delay circuit as claimed in claim 1, wherein said timing pulse generator comprises a shift register in which said input pulse sequence is shifted successively in response to said clock-pulses applied thereto at said repetition intervals, and a pair of exclusive OR gates, to which two successive shifted output signals are respectively applied in succession to each other from said shift register, for deriving respectively said latch signal and said reset signal in succession to each other, when said two successive shifted output signals are different from each other.
Claim 4
Dependent Claim
129 words
A clock-pulse reproduction circuit for reproducing a clock-pulse sequence corresponding to an input pulse sequence, wherein differential pulses corresponding respectively to each pulse of said input pulse sequence are successively gated by a gate pulse, which is formed by combining a first fixed rate delayed output pulse derived from a first fixed rate delay circuit as claimed in claim 1 in which said differential pulses are delayed at a first fixed rate of 1/2 m of said immediately preceding pulse interval, and a second fixed rate delayed output pulse derived from a second fixed rate delay circuit as claimed in claim 1 in which said differential pulses are delayed at a second fixed rate of (1-1/2 n ) of said immediately preceding pulse interval, m and n being integers.
Claim 5
Dependent Claim
18 words
A clock-pulse reproduction circuit as claimed in claim 3, wherein m and n are equal to each other.
Claim 6
Dependent Claim
106 words
A 2 N times frequency multiplying circuit, wherein a repetition frequency of a pulse sequence is multiplied by 2 N , comprising a series combination of N stages of twice frequency multiplying stages which comprise respectively a 1/2 rate delay circuit as claimed in claim 1 for delaying a respective input pulse sequence at the 1/2 rate, and an OR gate applied with said respective input pulse sequence and a delayed pulse sequence derived from said 1/2 rate delay circuit, so as to derive therefrom a respective output pulse sequence having a repetition frequency corresponding to twice the repetition frequency of said respective input pulse sequence.
Claim 7
Dependent Claim
159 words
A M times frequency multiplying circuit, wherein a repetition frequency of a pulse sequence is multiplied by an integer M, comprising a 2 N times frequency multiplying circuit as claimed in claim 5, which is applied with the input pulse sequence under the condition of N>M, a one K-th frequency dividing circuit which is reset by said input pulse sequence and applied with a pulse sequence having a repetition frequency corresponding to said 2 N times the repetition frequency of said input pulse sequence, which pulse sequence is derived from said 2 N times frequency multiplying circuit, under the condition of the smallest positive integer K being K≧2 N /M, and an OR gate which is applied with said input pulse sequence and another pulse sequence derived from said one K-th frequency dividing circuit, so as to derive therefrom an output pulse sequence having a repetition frequency corresponding to M-times of the repetition frequency of said input pulse sequence.
Claim 8
Dependent Claim
180 words
A frequency differential discriminator, wherein successive two pulse intervals of an input pulse sequence are compared with each other, so as to discriminate the variation of phase of a succeeding pulse in the input pulse sequence, comprising a pulse-interval sequence forming means for forming N series of successive pulse-interval sequences of said input pulse sequence, successive each one of which consists respectively of successive every other (N-1) pulse-intervals of said input pulse sequence, N fixed rate delay circuits as claimed in claim 1 for delaying leading and trailing edge pulses of each respective pulse-interval of said N series of successive pulse-interval sequences respectively at respective fixed rate of delay times being equal respectively to preceding pulse-intervals, an OR gate for forming a composite delayed edge pulse sequence which consists of a combination of respective delayed edge pulses derived from said N fixed rate delay circuits, and a phase comparator for effecting phase comparison between said composite delayed edge pulse sequence and said input pulse sequence, so as to discriminate the phase of the succeeding pulse in said input pulse sequence.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-08-22 | 1987-02-21 | 1987-08-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-08-22 | 1991-02-21 | 1991-08-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-08-22 | 1995-02-21 | 1995-08-23 | $7700.00 | Window Closed / Lapsed |