Patent US4398197A successfully refreshed from Google Patents.
US4398197A
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Digital sidelobe canceller with real weights
Assignee: United States Department of the Navy
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Filing: 1981-09-11
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Granted: 1983-08-09
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Expires: 2001-09-11
Abstract
Abstract The present invention is digital open-loop sidelobe canceller for decorreing signals by removing correlated components. The invention has inputs for receiving n pairs of digital sample values representing the digitized in-phase components and quadrature-phase components of the output of the main radar receiver and also of at least one auxiliary radar receiver. These data samples are stored in memory for later processing and are also furnished to computation networks which calculate weighting coefficients which are processed as real numbers. These real number weighting coefficients are utilized to subtract calculated real number values from the sample values representing the digitized in-phase and quadrature-phase components of the output of the main radar receiver.
Inventors
- 👤 George M. Dillard
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 14:20
CPC Classifications
H; H01; H01Q; H01Q3/00; H01Q3/26; H01Q3/2605; H01Q3/2611; H01Q3/2629; G; G01; G01S; G01S7/00; G01S7/02; G01S7/28; G01S7/2813
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
329 words
A real-weight digital open-loop coherent sidelobe canceller for a radar system having a main radar receiver and at least one auxiliary radar receiver comprising: a first memory having first and second inputs for receiving signals representing a sequence of n pairs of digital sample values, I mk and Q mk , the sample values I mk and Q mk representing, respectively, the digitized in-phase components and quadrature phase components of the output of the main radar receiver; a second memory having third and fourth inputs for receiving signals representing a sequence of n pairs of digital sample values I 1k and Q 1k , the sample values I 1k and Q 1k representing, respectively, the digitized in-phase components and quadrature phase components of the output of said auxiliary radar receiver; computing means connected to said first and second memories for forming signals representing the weighting coefficients W 1 , W 2 , V 1 and V 2 ; a first multiplier means connected to said computing means and to said second memory for forming signals representing the products W 1 I 1k ; a second multiplier means connected to said computing means and to said second memory for forming signals representing the products W 2 Q 1k ; a third multiplier means connected to said computing means and to said second memory for forming signals representing the products V 1 I 1k ; a fourth multiplier means connected to said computing means and to said second memory for forming signals the representing the products V 2 Q 1k ; and output means connected to said first memory and to said first, second, third and fourth multiplier means for forming a first signal set, I mk -[W 1 I 1k +W 2 Q 1k ], and a second signal set Q mk -[V 1 I 1k +V 2 Q 1k ] said first and second signal sets representing, respectively, sidelobe cancelled in-phase channel signals and sidelobe cancelled quadrature phase signals.
Claim 2
Dependent Claim
329 words
A real-weight digital open-loop coherent sidelobe canceller for a radar system having a main radar receiver and at least one auxiliary radar receiver comprising: a first memory having first and second inputs for receiving signals representing a sequence of n pairs of digital sample values, I mk and Q mk , the sample values I mk and Q mk representing, respectively, the digitized in-phase components and quadrature phase components of the output of the main radar receiver; a second memory having third and fourth inputs for receiving signals representing a sequence of n pairs of digital sample values I 1k and Q 1k , the sample values I 1k and Q 1k representing, respectively, the digitized in-phase components and quadrature phase components of the output of said auxiliary radar receiver; computing means connected to said first and second memories for forming signals representing the weighting coefficients W 1 , W 2 , V 1 and V 2 ; a first multiplier means connected to said computing means and to said second memory for forming signals representing the products W 1 I 1k ; a second multiplier means connected to said computing means and to said second memory for forming signals representing the products W 2 Q 1k ; a third multiplier means connected to said computing means and to said second memory for forming signals representing the products V 1 I 1k ; a fourth multiplier means connected to said computing means and to said second memory for forming signals the representing the products V 2 Q 1k ; and output means connected to said first memory and to said first, second, third and fourth multiplier means for forming a first signal set, I mk -[W 1 I 1k +W 2 Q 1k ], and a second signal set Q mk -[V 1 I 1k +V 2 Q 1k ] said first and second signal sets representing, respectively, sidelobe cancelled in-phase channel signals and sidelobe cancelled quadrature phase signals.
Claim 3
Dependent Claim
16 words
The sidelobe canceller of claim 1 wherein: said first and second memories are random access memories.
Claim 4
Dependent Claim
28 words
The sidelobe canceller of claims 1 or 2 wherein said computing means comprises: a first multiplier-accumulator; and a second multiplier-accumulator connected to the output of said first multiplier-accumulator.
Claim 5
Dependent Claim
62 words
The sidelobe canceller of claim 3 wherein: said first multiplier-accumulator forms signals representing the values A 1 , A 2 , A 3 , B 1 , B 2 , C 1 , and C 2 where ##EQU6## wherein said second multiplier-accumulator forms signals representing said weighting coefficients W 1 , W 2 , V 1 , and V 2 wherein ##EQU7##
Claim 6
Dependent Claim
62 words
The sidelobe canceller of claims 1 or 2 wherein said output means comprises: a first adder having inputs connected to said first and second multipliers; a second adder connected to said third and fourth multipliers; a first substractor connected to said first adder and to said first memory; and a second subtractor connected to said second adder and to said first memory.
Claim 7
Dependent Claim
60 words
The sidelobe canceller of claim 3 wherein said output means comprises: a first adder having inputs connected to said first and second multipliers; a second adder connected to said third and fourth multipliers; a first subtractor connected to said first adder and to said first memory; and a second subtractor connected to said second adder and to said first memory.
Claim 8
Dependent Claim
170 words
A real-weight digital open-loop coherent sidelobe canceller for a radar system having a main radar receiver and at least one auxiliary radar receiver comprising: memory means having a first input for receiving a first series of digital signals representing the in-phase channel components of the output of said main radar receiver and having a second input for receiving a second series of digital signals representing the quadrature phase channel components of the output of said main radar receiver, said memory means having first and second outputs, said memory means providing said first and second series of digital signals on said first and second outputs, respectively; and means connected to said at least one auxiliary receiver and to said memory means first and second outputs for subtracting from each of said first series of digital signals a signal representing one of a first series of real number weighted values and for subtracting from each of said second series of digital signals one of a second series of real number weighted values.
Claim 9
Dependent Claim
170 words
A real-weight digital open-loop coherent sidelobe canceller for a radar system having a main radar receiver and at least one auxiliary radar receiver comprising: memory means having a first input for receiving a first series of digital signals representing the in-phase channel components of the output of said main radar receiver and having a second input for receiving a second series of digital signals representing the quadrature phase channel components of the output of said main radar receiver, said memory means having first and second outputs, said memory means providing said first and second series of digital signals on said first and second outputs, respectively; and means connected to said at least one auxiliary receiver and to said memory means first and second outputs for subtracting from each of said first series of digital signals a signal representing one of a first series of real number weighted values and for subtracting from each of said second series of digital signals one of a second series of real number weighted values.
References Cited (Backward Citations)
US4119962A
Cited
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-08-08 | 1987-02-07 | 1987-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-08-08 | 1991-02-07 | 1991-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-08-08 | 1995-02-07 | 1995-08-09 | $7700.00 | Window Closed / Lapsed |