US4395812A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Forming an integrated circuit
Assignee: International Business Machines Corp
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Filing: 1981-06-05
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Granted: 1983-08-02
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Expires: 2001-06-05
Abstract
Abstract A high performance JFET structure and process are disclosed which are compatible with high performance NPN transistors. The high performance JFET is merged in a bipolar/FET device which forms a dense, two level logic function. The JFET can be employed as a switched device or as an active load in a bipolar logic circuit and is formed in the P-type base diffusion of what would otherwise have been an NPN transistor. In the BIFET merged device, the JFET and bipolar transistor share a common base and drain and a common collector and gate in the P-type base region of what would otherwise have been an NPN transistor. Both an NPN type BIFET and an PNP type BIFET are disclosed. The merged JFET and bipolar transistor provide better than a 30% area reduction when compared to their non-merged precursors.
Inventors
- 👤 David L. Bergeron
- 👤 Geoffrey B. Stephens
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:53
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/80; H10D30/83; H10D84/00; H10D84/01; H10D84/0107; H10D84/02; H10D84/03; H10D84/038; H10D84/40; H10D84/401; H10D84/403; H10D84/406; H10D84/409
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
142 words
In a process for forming an integrated circuit having a plurality of P-type regions formed in the same process step, a first subplurality of which are P-type base regions of vertical NPN transistors, a process for forming JFET device in one of the second subplurality of said plurality of P-type regions, comprising the steps of: forming an insulating layer on the surface of said base region having first and second windows therein; simultaneously forming first and second spaced apart N-type regions in said base region through said first and second windows for the JFET source and drain; and ion implanting an N-type channel region in said base region connected to said source and drain regions; said P-type base region serving as the gate for the JFET device; whereby a JFET device may be formed in the base region of an NPN transistor.
Claim 2
Dependent Claim
142 words
In a process for forming an integrated circuit having a plurality of P-type regions formed in the same process step, a first subplurality of which are P-type base regions of vertical NPN transistors, a process for forming JFET device in one of the second subplurality of said plurality of P-type regions, comprising the steps of: forming an insulating layer on the surface of said base region having first and second windows therein; simultaneously forming first and second spaced apart N-type regions in said base region through said first and second windows for the JFET source and drain; and ion implanting an N-type channel region in said base region connected to said source and drain regions; said P-type base region serving as the gate for the JFET device; whereby a JFET device may be formed in the base region of an NPN transistor.
Claim 3
Dependent Claim
129 words
The process of claim 1, which further comprises: forming one P-type region to extend horizontally beyond said first N-type region, with said first N-type region extending horizontally and vertically to separate said one P-type region into first and second P-type portions which are electrically isolated from one another, said first portion being said gate for said JFET device; forming a third window in said insulating layer over said second P-type portion; and forming a third N-type region through said third window, as an emitter in an NPN transistor formed with said second P-type portion as the base and said first N-type region serving as the collector thereof; whereby a series connected JFET and NPN bipolar transistor are formed with said first N-type diffusion serving as the output node thereof.
Claim 4
Dependent Claim
41 words
The process of claim 2 which further comprises: forming a conductor connecting said first P-type portion to said first N-type region; whereby said JFET operates as a self-biased load device connected in series with the collector of sand NPN bipolar transistor.
Claim 5
Dependent Claim
146 words
In a process for forming an integrated circuit having a plurality of P-type regions formed in the same process step, a first subplurality of which are P-type collector regions of graded base lateral PNP transistors, a process for forming a JFET device in one of a second subplurality of said plurality of P-type regions, comprising the steps of: forming an insulating layer on the surface of said collector region having first and second windows therein; simultaneously forming first and second spaced apart N-type regions in said base region through said first and second windows for JFET source and drain; and ion-implanting an N-type channel region in said collector region connected to said source and drain regions; said P-type collector region serving as the gate for the JFET device; whereby a JFET device may be formed in the collector region for a double diffused lateral PNP transistor.
Claim 6
Dependent Claim
146 words
In a process for forming an integrated circuit having a plurality of P-type regions formed in the same process step, a first subplurality of which are P-type collector regions of graded base lateral PNP transistors, a process for forming a JFET device in one of a second subplurality of said plurality of P-type regions, comprising the steps of: forming an insulating layer on the surface of said collector region having first and second windows therein; simultaneously forming first and second spaced apart N-type regions in said base region through said first and second windows for JFET source and drain; and ion-implanting an N-type channel region in said collector region connected to said source and drain regions; said P-type collector region serving as the gate for the JFET device; whereby a JFET device may be formed in the collector region for a double diffused lateral PNP transistor.
Claim 7
Dependent Claim
131 words
The process of claim 4, which further comprises: forming said one P-type region to extend horizontally beyond said first N-type region, said first N-type region extending horizontally and vertically to separate said one P-type region into first and second P-type portions which are electrically isolated from one another, said first portion being said gate for said JFET device; forming a third window in said insulating layer over said second P-type portions; and forming a third N-type region through said third window as a base region and a second P-type region through said third window and contained within said third N-type region as the emitter of a PNP lateral transistor, formed simultaneously with said second P-type portion as the collector thereof; whereby series connected JFET and lateral PNP bipolar transistors are formed.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-08-01 | 1987-01-31 | 1987-08-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-08-01 | 1991-01-31 | 1991-08-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-08-01 | 1995-01-31 | 1995-08-02 | $7700.00 | Window Closed / Lapsed |