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US4395098A Expired / Lapsed US ⏱️ 0.0 years remaining

Shutter time control circuit

Assignee: Canon Inc
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Filing: 1981-10-07
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Granted: 1983-07-26
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Expires: 2001-10-07
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Abstract

Abstract The present invention relates to a shutter time control circuit for a camera having a focal plane shutter and a timer circuit for counting the shutter time in a digital way. In accordance with the present invention a preset means for presetting the amount of the overlapping of the shutter curtain and/or the response delay of the magnet on the timer circuit as digital values is provided in such a manner that the clock time is compensated in accordance with the preset digital value so as to compensate the exposure error due to the overlapping amount of the shutter curtains and so on, which makes it possible to offer a digital exposure compensation device suited for the camera having a shutter control circuit for digitally controlling the shutter time.

Inventors

  • 👤 Masanori Uchidoi
  • 👤 Kazunobu Urushihara

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 13:29
CPC Classifications
G; G03; G03B; G03B7/00; G03B7/08; G03B7/081; G03B7/083

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 211 words
A shutter control circuit for a shutter having a mechanical condition producing a delay, comprising: (a) a counter circuit for counting pulses when a shutter release operation is performed; (b) a shutter time information circuit for producing a digital value corresponding to an exposure time; (c) preset means having impedance means for adjustably presetting time information corresponding to a mechanical condition of the shutter mechanism; (d) converting means for converting the time information preset by said impedance means into a digital value; (e) a shutter time information setting circuit including a first part coupled to said shutter time information circuit for setting said digital value from the shutter time information circuit and a second part coupled to said converting means for setting said digital value from the converting means; (f)a shutter time control circuit coupled to said counter circuit and the first and second parts of said shutter time information setting circuit, said shutter time control circuit forming a shutter closing signal when the value counted by said counter circuit has assumed a value corresponding to the sum of the digital values set by said first and second parts of the shutter time information setting circuit; and (g) shutter control means for closing the shutter in response to the closing signal.
Claim 2
Dependent Claim 211 words
A shutter control circuit for a shutter having a mechanical condition producing a delay, comprising: (a) a counter circuit for counting pulses when a shutter release operation is performed; (b) a shutter time information circuit for producing a digital value corresponding to an exposure time; (c) preset means having impedance means for adjustably presetting time information corresponding to a mechanical condition of the shutter mechanism; (d) converting means for converting the time information preset by said impedance means into a digital value; (e) a shutter time information setting circuit including a first part coupled to said shutter time information circuit for setting said digital value from the shutter time information circuit and a second part coupled to said converting means for setting said digital value from the converting means; (f)a shutter time control circuit coupled to said counter circuit and the first and second parts of said shutter time information setting circuit, said shutter time control circuit forming a shutter closing signal when the value counted by said counter circuit has assumed a value corresponding to the sum of the digital values set by said first and second parts of the shutter time information setting circuit; and (g) shutter control means for closing the shutter in response to the closing signal.
Claim 3
Dependent Claim 218 words
A shutter control circuit for a shutter having a mechanical condition producing a delay, comprising: (a) a counter circuit for counting pulses when a shutter release operation is performed; (b) preset means having impedance means for adjustably presetting time information corresponding to a mechanical condition of the shutter mechanism; (c) detecting means for producing a detecting signal when the value counted by said counter circuit has assumed a value corresponding to said impedance means; (d) a shutter time information setting circuit including a first part for setting a digital value corresponding to the exposure time and a second part to which the output of said counter circuit is connected, said second part being responsive to the output of said detecting means arranged for setting a digital value corresponding to the content of the counter when said detecting means produces an output; (e) a shutter time control circuit coupled to said counter circuit and the first and second parts of said shutter time information setting circuit for forming a shutter closing signal when the value counted by said counter circuit has assumed a value corresponding to the sum of the digital values set by said first and second parts of the shutter time information setting circuit; and (f) means for closing the shutter in response to the closing signal.
Claim 4
Dependent Claim 218 words
A shutter control circuit for a shutter having a mechanical condition producing a delay, comprising: (a) a counter circuit for counting pulses when a shutter release operation is performed; (b) preset means having impedance means for adjustably presetting time information corresponding to a mechanical condition of the shutter mechanism; (c) detecting means for producing a detecting signal when the value counted by said counter circuit has assumed a value corresponding to said impedance means; (d) a shutter time information setting circuit including a first part for setting a digital value corresponding to the exposure time and a second part to which the output of said counter circuit is connected, said second part being responsive to the output of said detecting means arranged for setting a digital value corresponding to the content of the counter when said detecting means produces an output; (e) a shutter time control circuit coupled to said counter circuit and the first and second parts of said shutter time information setting circuit for forming a shutter closing signal when the value counted by said counter circuit has assumed a value corresponding to the sum of the digital values set by said first and second parts of the shutter time information setting circuit; and (f) means for closing the shutter in response to the closing signal.
Claim 5
Dependent Claim 227 words
A shutter control circuit for a shutter having a mechanical condition producing a delay, comprising: (a) a counter circuit for counting pulses when a shutter release operation is performed; (b) preset means having impedance means for adjustably presetting time information corresponding to a mechanical condition of the shutter mechanism; (c) a timer for counting the time and producing an output after counting the time corresponding to the impedance of said impedance means, said timer being arranged to be actuated by the shutter release operation; (d) a shutter time information setting circuit including a first part for setting a digital value corresponding to the exposure time and a second part to which the output of said counter circuit is connected, said second part being responsive to the output of said timer and arranged for setting a digital value corresponding to the content of the counter when said timer produces an output; (e) a shutter time control circuit coupled to said counter circuit and the first and second parts of said shutter time information setting circuit for forming a shutter closing signal when the value counted by said counter circuit has assumed a value correspoding to the sum of the digital values set by said first and second parts of the shutter time information setting circuit; and (f) means for closing the shutter in response to the closing signal.
Claim 6
Dependent Claim 227 words
A shutter control circuit for a shutter having a mechanical condition producing a delay, comprising: (a) a counter circuit for counting pulses when a shutter release operation is performed; (b) preset means having impedance means for adjustably presetting time information corresponding to a mechanical condition of the shutter mechanism; (c) a timer for counting the time and producing an output after counting the time corresponding to the impedance of said impedance means, said timer being arranged to be actuated by the shutter release operation; (d) a shutter time information setting circuit including a first part for setting a digital value corresponding to the exposure time and a second part to which the output of said counter circuit is connected, said second part being responsive to the output of said timer and arranged for setting a digital value corresponding to the content of the counter when said timer produces an output; (e) a shutter time control circuit coupled to said counter circuit and the first and second parts of said shutter time information setting circuit for forming a shutter closing signal when the value counted by said counter circuit has assumed a value correspoding to the sum of the digital values set by said first and second parts of the shutter time information setting circuit; and (f) means for closing the shutter in response to the closing signal.
Claim 7
Dependent Claim 180 words
A shutter control circuit for a shutter having a mechanical condition producing a delay, comprising: (a) a counter circuit for counting pulses when a shutter release operation is performed; (b) preset means having impedance means for adjustably presetting time information corresponding to a mechanical condition of the shutter mechanism; (c) a shutter time information setting circuit including a first part for setting a digital value corresponding to the exposure time and a second part, said second part having converting means for converting the time information preset by said impedance means into a digital value and setting the digital value converted by said converting means; (d) a shutter time control circuit coupled to said counter circuit and the first and second parts of said shutter time information setting circuit for forming a shutter closing signal when the value counted by said counter circuit has assumed a value corresponding to the sum of digital values set by said first and second parts of the shutter time information setting circuit; and (e) means for closing the shutter in response to the closing signal.
Claim 8
Dependent Claim 180 words
A shutter control circuit for a shutter having a mechanical condition producing a delay, comprising: (a) a counter circuit for counting pulses when a shutter release operation is performed; (b) preset means having impedance means for adjustably presetting time information corresponding to a mechanical condition of the shutter mechanism; (c) a shutter time information setting circuit including a first part for setting a digital value corresponding to the exposure time and a second part, said second part having converting means for converting the time information preset by said impedance means into a digital value and setting the digital value converted by said converting means; (d) a shutter time control circuit coupled to said counter circuit and the first and second parts of said shutter time information setting circuit for forming a shutter closing signal when the value counted by said counter circuit has assumed a value corresponding to the sum of digital values set by said first and second parts of the shutter time information setting circuit; and (e) means for closing the shutter in response to the closing signal.
Claim 9
Dependent Claim 58 words
A shutter control circuit according to claims 1, 2, 3, or 4, wherein said shutter time control circuit is arranged to compare the content of said counter and the sum of the digital values set by said first and second parts and forms said shutter closing signal when the former has assumed a predetermined relation to the latter.

References Cited (Backward Citations)

US3683767A Cited
US4034383A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1986-07-25 1987-01-24 1987-07-26 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1990-07-25 1991-01-24 1991-07-26 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1994-07-25 1995-01-24 1995-07-26 $7700.00 Window Closed / Lapsed

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