Decoding and selection circuit for a monolithic memory

Claim 2

A selection circuit for a memory array having a matrix of cells arranged in n rows and m columns wherein the cells of different rows are connected to n word lines each having selected and non-selected states, the selection of a word line during a selected state being controlled by an address decoding circuit receiving at its input a line addressing signal and having n outputs, each output controlling the state of a line driver transistor, the n driver transistors being of a first conductivity type, each of which includes first and second electrodes and a control electrode, said first electrode being connected to a voltage supply terminal, said second electrode being connected to a word line and said control electrode being connected to an output of said decoding circuit, comprising; n control transistors having a conductivity opposite to that of said driver transistors, each of said control transistors being associated with one of said driver transistors and having a first conductive electrode connected to said voltage supply terminal and a second conductive electrode connected to the control electrode of its associated driver transistor, and means including a regulating transistor for supplying a current to the control electrode of each of said control transistors during the selected and non-selected states of an associated word line.

Claim 3

A selection circuit as set forth in claim 1 wherein each of said driver transistors is of the NPN type and each of the control transistors is of the PNP type.

Claim 4

A selection circuit as set forth in claim 2 wherein the collectors of said driver transistors and the emitters of the control transistors are connected to said voltage supply terminal, the emitters of said driver transistors are connected to the word lines and the bases of said driver transistors are connected to the outputs of said decoding circuit and to the collectors of said control transistors.

Claim 5

A selection circuit for a memory array having a matrix of cells arranged in n rows and m columns wherein the cells of different rows are connected to n word lines, the selection of a word line being controlled by an address decoding circuit receiving at its input a line addressing signal and having n outputs, each output controlling the state of a line driver transistor, the n driver transistors each being of the NPN type, each of which includes a collector, an emitter and a base, said collector being connected to a voltage supply terminal, said emitter being connected to a word line and said base being connected to an output of said decoding circuit, comprising; n control transistors each being of the PNP type, each of said control transistors being associated with one of said driver transistors and having an emitter connected to said voltage supply terminal and a collector connected to the base of its associated driver transistor, and means for supplying a current to the control electrode of each of said control transistors, said means including a regulating transistor having a conductivity type similar to that of said control transistors and connected so as to form a current mirror with said control transistors, said regulating transistor having its base connected to the base of at least one of said control transistors, its emitter connected to said voltage supply terminal and its collector connected to its base and to a controllable current source.

Claim 6

A selection circuit for a memory array having a matrix of cells arranged in n rows and m columns wherein the cells of different rows are connected to n word lines, the selection of a word line being controlled by an address decoding circuit receiving at its input a line addressing signal and having n outputs, each output controlling the state of a line driver transistor, the n driver transistors each being of the NPN type, each of which includes a collector, an emitter and a base, said collector being connected to a voltage supply terminal, said emitter being connected to a word line and said base being connected to an output of said decoding circuit, comprising; n control transistors each being of the PNP type, each of said control transistors being associated with one of said driver transistors and having an emitter connected to said voltage supply terminal and a collector connected to the base of its associated driver transistor, and means for supplying a current to the control electrode of each of said control transistors, said means including a regulating transistor having a conductivity type similar to that of said control transistors and connected so as to form a current mirror with said control transistors, said regulating transistor having its base connected to the base of at least one of said control transistors, its emitter connected to said voltage supply terminal and its collector connected to its base and to a controllable current source.

Claim 7

A selection circuit as set forth in claim 4 wherein said control transistors are arranged into k groups of p elements, with k·p=n and with the bases of the control transistors of one group being interconnected, and further including k regulating transistors, each of said k regulating transistors having its base connected to the interconnected bases of one group of said control transistors.

Claim 8

A selection circuit as set forth in claim 5 further including a plurality of controllable current sources, each of said current sources being associated with a respective one of said regulating transistors, each of said current sources including a transistor having a first electrode connected to the collector of the associated regulating transistor, a second electrode connected via a resistor to a second voltage supply terminal and a control electrode connected to a generator producing a reference voltage.

Claim 9

A selection circuit as set forth in claim 6 wherein each current source transistor is an NPN type transistor having a collector connected to the collector of its associated regulating transistor, an emitter connected via said resistor to said second voltage supply terminal and a base connected to said reference voltage generator.

Claim 10

A selection circuit as set forth in claim 7 wherein said reference voltage generator includes a current mirror including first and second transistors of the same type and having similar characteristics to those of said control transistors, said first transistor having its base and collector interconnected and connected via a first resistor to said second voltage supply terminal and its emitter connected to said first voltage supply terminal, said second transistor having its base connected to the base of said first transistor, its emitter connected to said first voltage supply terminal and its collector connected via a second resistor to said second voltage supply terminal, said second resistor having a resistance value equal to that of said first resistor, and output circuit means coupled to the collector of said second transistor for generating said reference voltage.