Semiconductor integrated circuit device

Claim 2

A semiconductor integrated circuit device comprising a power amplifier circuit including a vertical type PNP transistor and a first NPN transistor which are formed in a common semiconductor substrate, the output stage of said power amplifier circuit comprising a complementary symmetrical circuit wherein an output terminal is led out of the connection point between the collector of said vertical type PNP transistor and the collector of said first NPN transistor, a d.c. power source is connected between said emitter of said vertical type PNP transistor and the emitter of said first NPN transistor, and wherein at least one of the transistors constituting said complementary symmetrical circuit forms a current mirror circuit together with an additional transistor.

Claim 3

A semiconductor integrated circuit device comprising a power amplifier circuit including a vertical type PNP transistor and a first NPN transistor which are formed in a common semiconductor substrate, the output stage of said power amplifier circuit comprising a complementary symmetrical circuit wherein an output terminal is led out of the connection point between the collector of said vertical type PNP transistor and the collector of said first NPN transistor, and a negative d.c. power source is supplied to the emitter of said first NPN transistor, and wherein at least one of the transistors constituting said complementary symmetrical circuit forms a current mirror circuit together with an additional transistor.

Claim 4

A semiconductor integrated circuit device comprising a power amplifier circuit including a vertical type PNP transistor and a first NPN transistor which are formed in a common semiconductor substrate, the output stage of said power amplifier circuit comprising a complementary symmetrical circuit wherein an output terminal is led out of the connection point between the collector of said vertical type PNP transistor and the collector of said first NPN transistor, and a negative d.c. power source is supplied to the emitter of said first NPN transistor, and wherein at least one of the transistors constituting said complementary symmetrical circuit forms a current mirror circuit together with an additional transistor.

Claim 5

A semiconductor integrated circuit device according to any one of claims 4 and 5, wherein said vertical type PNP transistor and a second PNP transistor form a first current mirror circuit and said first NPN transistor and a second NPN transistor form a second current mirror circuit; and wherein the emitter area ratio of the transistors constituting the first current mirror circuit is made equal to the emitter area ratio of the transistors constituting the second current mirror circuit.

Claim 6

A semiconductor integrated circuit device according to claims 1 or 2 wherein each of the transistors constituting said complementary symmetrical circuit forms a current mirror circuit together with an additional transistor.

Claim 7

A semiconductor integrated circuit device comprising a power amplifier circuit including a vertical type PNP transistor and a first NPN transistor which are formed in a common semiconductor substrate, the output stage of said power amplifier circuit comprising a complementary symmetrical circuit wherein an output terminal is led out of the connection point between the collector of said vertical type PNP transistor and the collector of said first NPN transistor, the emitter of said vertical type PNP transistor being connected to a first reference potential, and the emitter of said first NPN transistor being connected to a second reference potential, and wherein at least one of the transistors constituting said complementary symmetrical circuit forms a current mirror circuit.

Claim 8

A semiconductor integrated circuit device comprising a power amplifier circuit including a vertical type PNP transistor and a first NPN transistor which are formed in a common semiconductor substrate, the output stage of said power amplifier circuit comprising a complementary symmetrical circuit wherein an output terminal is led out of the connection point between the collector of said vertical type PNP transistor and the collector of said first NPN transistor, the emitter of said vertical type PNP transistor being connected to a first reference potential, and the emitter of said first NPN transistor being connected to a second reference potential, and wherein at least one of the transistors constituting said complementary symmetrical circuit forms a current mirror circuit.

Claim 9

A semiconductor integrated circuit device according to claim 5 where said first reference potential is provided by a first DC voltage source and said second reference potential is provided by a second DC voltage source.

Claim 10

A semiconductor integrated circuit device according to claims 5, or 6, wherein said vertical type PNP transistor and a second PNP transistor form a first current mirror circuit and said first NPN transistor and a second NPN transistor form a second current mirror circuit; and wherein the emitter area ratio of the transistors constituting the first current mirror circuit is made equal to the emitter area ratio of the transistors constituting the second current mirror circuit.

Claim 11

A semiconductor integrated circuit device according to claims 5, or 6 wherein each of the transistors constituting said complementary symmetrical circuit forms a current mirror circuit together with an additional transistor.

Claim 12

A low frequency amplifier circuit comprising vertical type PNP transistors and NPN transistors formed in a common semiconductor substrate, wherein the emitter of a first one of said vertical PNP transistors is connected to a first terminal; the collector of said first vertical type PNP transistor and that of a first one of said NPN transistors are connected to provide an output terminal; a first resistor is connected at one end to said first terminal, the other end said first resistor being connected to the collector of a second one of said NPN transistors; the emitter of said second NPN transistor and that of a second one of said vertical type PNP transistors are connected to a third terminal; a second resistor is connected at one end to the collector of said second vertical type PNP transistor, the other end of said second resistor being connected to said second terminal; the base of said first vertical type PNP transistor is connected to the connection point between said first resistor and the collector of said second NPN transistor; the base of said first NPN transistor is connected to the connection point between said second resistor and the collector of said second vertical type PNP transistor; a first DC voltage source is connected between said first terminal and said second terminal; and a second DC voltage source is connected between said second terminal and said third terminal.

Claim 13

A low frequency amplifier circuit comprising vertical type PNP transistors and NPN transistors formed in a common semiconductor substrate, wherein the emitter of a first one of said vertical PNP transistors is connected to a first terminal; the collector of said first vertical type PNP transistor and that of a first one of said NPN transistors are connected to provide an output terminal; a first resistor is connected at one end to said first terminal, the other end said first resistor being connected to the collector of a second one of said NPN transistors; the emitter of said second NPN transistor and that of a second one of said vertical type PNP transistors are connected to a third terminal; a second resistor is connected at one end to the collector of said second vertical type PNP transistor, the other end of said second resistor being connected to said second terminal; the base of said first vertical type PNP transistor is connected to the connection point between said first resistor and the collector of said second NPN transistor; the base of said first NPN transistor is connected to the connection point between said second resistor and the collector of said second vertical type PNP transistor; a first DC voltage source is connected between said first terminal and said second terminal; and a second DC voltage source is connected between said second terminal and said third terminal.

Claim 14

A low frequency amplifier circuit according to claim 9, wherein the emitter of said first vertical type PNP transistor and that of a third one of said vertical type PNP transistors are connected to each other; the base and collector of said third vertical type PNP transistor are connected to the base of said first vertical type PNP transistor to form a first current mirror circuit; the emitter of said first NPN transistor and that of said third NPN transistor are connected to each other; and the collector and base of said third NPN transistor are connected to the base of said first NPN transistor to form a second current mirror circuit.

Claim 15

A low frequency amplifier circuit according to claim 10, wherein the emitter area ratio of said first and third vertical PNP transistors forming said first current mirror circuit is made equal to the emitter area ratio of said first and third NPN transistors forming said second current mirror circuit.

Claim 16

A low frequency amplifier circuit comprising vertical type PNP transistors and NPN transistors formed in a common semiconductor substrate, wherein the emitter of a first one of said vertical PNP transistors is connected to a first terminal; the collector of said first vertical type PNP transistor and that of a first one of said NPN transistors are connected to provide an output terminal; a first resistor is connected at one end to said first terminal, the other end said first resistor being connected to the collector of a second one of said NPN transistors; the emitter of said second NPN transistor and that of a second one of said vertical type PNP transistors are connected to a third terminal; a second resistor is connected at one end to the collector of said second vertical type PNP transistor, the other end of said second resistor being connected to said second terminal; the base of said first vertical type PNP transistor is connected to the connection point between said first resistor and the collector of said second NPN transistor; the base of said first NPN transistor is connected to the connection point between said second resistor and the collector of said second vertical type PNP transistor; said first terminal being connected to a first reference potential; said second terminal being connected to a second reference potential; and said third terminal being connected to a third reference potential.

Claim 17

A low frequency amplifier circuit comprising vertical type PNP transistors and NPN transistors formed in a common semiconductor substrate, wherein the emitter of a first one of said vertical PNP transistors is connected to a first terminal; the collector of said first vertical type PNP transistor and that of a first one of said NPN transistors are connected to provide an output terminal; a first resistor is connected at one end to said first terminal, the other end said first resistor being connected to the collector of a second one of said NPN transistors; the emitter of said second NPN transistor and that of a second one of said vertical type PNP transistors are connected to a third terminal; a second resistor is connected at one end to the collector of said second vertical type PNP transistor, the other end of said second resistor being connected to said second terminal; the base of said first vertical type PNP transistor is connected to the connection point between said first resistor and the collector of said second NPN transistor; the base of said first NPN transistor is connected to the connection point between said second resistor and the collector of said second vertical type PNP transistor; said first terminal being connected to a first reference potential; said second terminal being connected to a second reference potential; and said third terminal being connected to a third reference potential.

Claim 18

A semiconductor integrated circuit device according to claim 12 where said first reference potential is provided by a first DC voltage source; said second reference potential is ground; and said third reference potential is provided by a second DC voltage source.

Claim 19

A semiconductor integrated circuit device according to claim 12 where said first reference potential is provided by a first DC voltage source; said second reference potential is provided by a second DC voltage source; and said third reference potential is ground.

Claim 20

A low frequency amplifier circuit according to claims 12, 13 or 14, wherein the emitter of said first vertical type PNP transistor and that of a third one of said vertical type PNP transistors are connected to each other; the base and collector of said third vertical type PNP transistor are connected to the base of said first vertical type PNP transistor to form a first current mirror circuit; the emitter of said first NPN transistor and that of said third NPN transistor are connected to each other; and the collector and base of said third NPN transistor are connected to the base of said first NPN transistor to form a second current mirror circuit.

Claim 21

A low frequency amplifier circuit according to claim 15 wherein the emitter area ratio of said first and third vertical PNP transistors forming said first current mirror circuit is made equal to the emitter area ratio of said first and third NPN transistors forming said second current mirror circuit.