Shift register

Claim 2

A shift register of the type capable of performing shift operations by changing the access of a random access memory comprising: a random access memory having a memory capacity of 2 k words, where 2 k ≧n and n is the number of steps required for said shift register; a k-bit counter adapted to perform a counting operation when a clock pulse is input thereof an then to input, via a k-bit operation unit, the count output to said random access memory as an address for writing an input data in said random access memory; and wherein said k-bit operation unit is adapted to perform an operation with respect to said count output of said k-bit counter and the address of desired shifted data and then to output the operated result as an address for reading said shifted data from said random access memory, whereby high speed reading operation of said shifted data is attained.

Claim 3

A shift register as claimed in claim 1, wherein said k-bit counter is a down-counter which is counted down by a clock pulse input thereto, and said k-bit operation unit is a k-bit adder.

Claim 4

A shift register as claimed in claim 1, wherein said k-bit counter is an up-counter which is counted up by a clock pulse input thereto, and said k-bit operation unit is a k-bit subtracter.

Claim 5

A shift register of the type capable of performing shift operations by changing the access of a random access memory comprising: 2 n words, where n is the number of steps required for said shift register; a counter, the input of which is a clock pulse; a sequence control signal generation means for generating a sequence control signal in accordance with each clock pulse input thereto; a constant generation means for generating successively a first constant 0 and a second constant n in accordance with said sequence control signal and, in the absence of the input of said sequence control signal, generating the address of desired shifted data (SFTD DATA) input to said constant generation means as is; and an operation means for performing an operation with respect to either one of said first and second constants 0 and n, which are outputs of said constant generation means, and with respect to the output of said counter so as to generate first and second addresses successively for writing an input data in different addresses of said random access memory twice when the clock pulse is input thereto, whereby high speed reading operations of said shifted data is attained.

Claim 6

A shift register of the type capable of performing shift operations by changing the access of a random access memory comprising: 2 n words, where n is the number of steps required for said shift register; a counter, the input of which is a clock pulse; a sequence control signal generation means for generating a sequence control signal in accordance with each clock pulse input thereto; a constant generation means for generating successively a first constant 0 and a second constant n in accordance with said sequence control signal and, in the absence of the input of said sequence control signal, generating the address of desired shifted data (SFTD DATA) input to said constant generation means as is; and an operation means for performing an operation with respect to either one of said first and second constants 0 and n, which are outputs of said constant generation means, and with respect to the output of said counter so as to generate first and second addresses successively for writing an input data in different addresses of said random access memory twice when the clock pulse is input thereto, whereby high speed reading operations of said shifted data is attained.

Claim 7

A shift register as claimed in claim 4, wherein said constant generation means comprises a plurality of AND gates which are inhibited by a first sequence control signal which is input thereto from said sequence control signal generation means, the input to said AND gates being the address of said shifted data, and a plurality of OR gates, one input to said OR gates being at least one output from said plurality of AND gates, and the other input to said OR gates being a second sequence control signal from said sequence control signal generation means.