EPROM and RAM cell layout with equal pitch for use in fault tolerant memory device or the like

Claim 2

A fault tolerant semiconductor memory device formed in a face of a semiconductor body comprising: a data memory array at said face composed of rows and columns of read/write memory cells, and a plurality programmable cells laid out at said face in rows of the same pitch as and aligned with said rows of the data memory array, each of the programmable cells being individually programmed to retain indefinitely an indication of a faulty cell present in the aligned row of memory cells, and at least one row of redundant cells for replacing one of said rows of memory cells containing a faulty cell in response to the programmable cell for such row being programmed.

Claim 3

A device according to claim 1 wherein said memory cells are one-transistor type dynamic read/write memory cells.

Claim 4

A device according to claim 1 wherein said programmable cells are floating gate type electrically programmable cells including floating gates partly over the current paths and partly beneath the row lines.

Claim 5

A semiconductor memory device comprising: a data memory array of rows and columns of one-transistor type dynamic read/write memory cells, and a plurality of columns of programmable cells laid out in rows of the same pitch as and aligned with said rows of the data memory, the programmable cells including row lines and current paths laterally spaced from the row lines, the programmable cells being floating gate type electrically programmable cells including floating gates partly over the current paths and partly beneath the row lines, and means to receive an address and to decode a part of said address to simultaneously activate for access one row line of the data memory array and the same one row line for the programmable cells.

Claim 6

A semiconductor memory device comprising: a data memory array of rows and columns of one-transistor type dynamic read/write memory cells, and a plurality of columns of programmable cells laid out in rows of the same pitch as and aligned with said rows of the data memory, the programmable cells including row lines and current paths laterally spaced from the row lines, the programmable cells being floating gate type electrically programmable cells including floating gates partly over the current paths and partly beneath the row lines, and means to receive an address and to decode a part of said address to simultaneously activate for access one row line of the data memory array and the same one row line for the programmable cells.

Claim 7

A memory device according to claim 4 wherein said one row line in the form of an elongated continuous conductive strip is connected to the gate of a transistor in each memory cell for such row and is also connected to the control gate of a floating gate type transistor in each of the programmable cells in such row.

Claim 8

A memory device according to claim 5 wherein the row lines for adjacent rows are about the same distance apart as the width of each such row line.

Claim 9

A fault tolerant semiconductor memory formed in a face of a semiconductor body comprising: a data memory array of rows and columns of memory cells at said face; a plurality of substitute memory cells at said face aligned with the rows of the data memory array and having the same pitch; a plurality of row lines at said face each making connection to all memory cells and substitute cells in a row; fault-address storage means at said face including at least one column of programmable cells aligned with said rows of the data memory array and having the same pitch; each programmable cell being connected to one of the row lines and including a current path spaced from the row line; means at said face to receive an address and to select one of said rows for access based on said address and at the same time to select said row line in the fault-address storage means; means at said face to connect an output from the data memory array to an output means of the device if the selected part of the fault-address storage means does not indicate a fault at the selected location or to connect an output from the substitute memory cells to said output means if the selected part of the fault-address storage means does indicate a fault at the addressed location.

Claim 10

A fault tolerant semiconductor memory formed in a face of a semiconductor body comprising: a data memory array of rows and columns of memory cells at said face; a plurality of substitute memory cells at said face aligned with the rows of the data memory array and having the same pitch; a plurality of row lines at said face each making connection to all memory cells and substitute cells in a row; fault-address storage means at said face including at least one column of programmable cells aligned with said rows of the data memory array and having the same pitch; each programmable cell being connected to one of the row lines and including a current path spaced from the row line; means at said face to receive an address and to select one of said rows for access based on said address and at the same time to select said row line in the fault-address storage means; means at said face to connect an output from the data memory array to an output means of the device if the selected part of the fault-address storage means does not indicate a fault at the selected location or to connect an output from the substitute memory cells to said output means if the selected part of the fault-address storage means does indicate a fault at the addressed location.

Claim 11

A device according to claim 7 wherein said memory cells are read/write memory cells, the substitute memory cells are a column of read/write memory cells, the programmable cells are floating gate type field-effect transistors, and each row line is a continuous conductive strip crossing the memory array and the programmable cells.

Claim 12

A fault tolerant memory device formed in a face of a semiconductor body comprising an array of rows and columns of memory cells at said face of the semiconductor body, means at said face for addressing locations in the array, at least one row or column of redundant cells at said face and means at said face for accessing said redundant cells when defective cells are at the location addressed in the array, and a plurality of electrically programmable elements at said face aligned with said rows of memory cells for storing the locations of said defective cells, each of said elements having a plurality of conductive layers in each of said memory cells, row lines connected to rows of cells in said array and also extending across said programmable elements and making contact thereto.

Claim 13

A fault tolerant memory device formed in a face of a semiconductor body comprising an array of rows and columns of memory cells at said face of the semiconductor body, means at said face for addressing locations in the array, at least one row or column of redundant cells at said face and means at said face for accessing said redundant cells when defective cells are at the location addressed in the array, and a plurality of electrically programmable elements at said face aligned with said rows of memory cells for storing the locations of said defective cells, each of said elements having a plurality of conductive layers in each of said memory cells, row lines connected to rows of cells in said array and also extending across said programmable elements and making contact thereto.

Claim 14

A device according to claim 9 wherein the memory cells are dynamic read/write one-transistor cells and the conductive layers include two overlapping layers of polycrystalline silicon.

Claim 15

A device according to claim 10 wherein the electrically programmable elements are floating gate type EPROM cells each having two overlapping conductive layers forming a control gate and a floating gate.

Claim 16

A device according to claim 11 wherein each EPROM cell has a channel laterally spaced from the control gate.