Random access memory preset circuitry

Claim 1

Circuitry for presetting a bipolar random access memory, said memory including a plurality of memory cells in a matrix of columns and rows, each of said plurality of cells including a bistable flip-flop with each of the inverters of said flip-flop having first and second emitters, the first emitters of all memory cells in each row of said matrix being coupled together and to a bottom word line terminating in a first grounded current source, the second emitters of all memory cells in each column being coupled to one of a plurality of bit line pairs, each bit line inset pairs being terminated in a second grounded current source, each of said bit line pairs being coupled to a bit line clamping circuit, said memory presetting circuitry comprising: reset signal input circuitry for producing a high output signal during operation of said memory and a low output signal for presetting said memory; first circuit means interposed between each bottom word line and its respective first grounded current source, and responsive to said low output signal for breaking the circuit between said word line and its current source and for applying V cc to each of said word lines; second circuit means coupled between each bit line clamping circuit and its respective power source, said second circuit means responsive to said low output signal for disabling said clamping circuit; third circuit means coupled to each bit line in each pair of said plurality of bit line pairs, said third circuit means responsive to said low output signal for drawing current from said bit line; and read/write control means interposed between each bit line and a positive voltage source for selectively applying said positive voltage to one bit line in each of said pairs.