Offset compensation for switched capacitor integrators

Claim 1

An integrator containing an integrator input terminal and an integrator output terminal comprising: an operational amplifier having an inverting input lead, a non-inverting input lead, and an output lead, said operational amplifier producing an offset voltage on said output lead; a first switch means responsive to a first phase of a signal having two phases, said first switch means connected between said inverting input lead and said output lead; a first capacitor, having a capacitance C 1 , having a first and a second plate, said first plate connected to said inverting input lead of said operational amplifier; a second switch means, responsive to a second phase of said signal having two phases, said second switch means connected between said second plate of said first capacitor and said output lead of said operational amplifier; a second capacitor, having capacitance value α 2 C 1 , having a first and a second plate, said first plate connected to said inverting input lead of said operational amplifier; third switch means, responsive to said second phase, said switch means connected between said second plate of said second capacitor and said output lead of said operational amplifier; a fourth switch means, responsive to said first phase, said fourth switch means connected between said second plate of said second capacitor and a voltage reference; and switched capacitor means connected between said inverting input lead and said integrator input terminal, said switched capacitor means serving as a resistor equivalent and including a third capacitor having a first and a second plate, said third capacitor having capacitance α 1 C 1 ; whereby the effect of said offset voltage on the integrator output voltage available on said output terminal is eliminated by the simultaneous integration of said input voltage and said offset voltage during the period when said first clock phase is low and said second clock phase is high.