Patent US4393346A successfully refreshed from Google Patents.
US4393346A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Voltage controlled resistor
Assignee: Circuit Research Labs Inc
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Filing: 1981-07-06
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Granted: 1983-07-12
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Expires: 2001-07-06
Abstract
Abstract A voltage controlled resistor includes an operational transconductance amplifier (OTA) including first and second linearizing diodes which not only optimize signal-to-noise distortion levels but also represent the AC impedance from the inverting input to ground. The OTA turns on and off in response to the amount of gain control current being supplied thereto. A Darlington transistor is coupled to the output of the OTA for providing a low impedance buffered output. A first resistor provides current flow through the diodes. A feedback resistor supplies and controls bias current to one of the diodes. A third resistor maintains bias to the Darlington pair when the OTA output approaches open circuit output impedance conditions.
Inventors
- 👤 Ronald R. Jones
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:46
CPC Classifications
H; H03; H03H; H03H11/00; H03H11/46
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
221 words
A voltage controlled resistor circuit, comprising: an operational transconductance amplifier having an inverting input, a non-inverting input adpated to be coupled to a first source of supply voltage, a diode bias input, a bias input for receiving a gain control current, first and second power supply terminals adapted to be coupled to second and third supply voltages, respectively, and an output for exibiting a high output impedance when the gain control current is substantially zero, said output impedance decreasing as said gain control current increases, said operational transconductance amplifier having first and second linearizing diodes each having an anode coupled to said diode bias input, said first linearizing diode having a cathode coupled to said inverting input and said second linearizing diode having a cathode coupled to said non-inverting input; first means coupled to said output for providing a low impedance buffered output; first impedance means coupled to said diode bias input for producing current flow through said first and second linearizing diodes; second impedance means coupled to said low impedance buffered output for providing feedback to said inverting input and for supplying and controlling bias current to said first linearizing diode; and third impedance means coupled between said output and said diode bias input for maintaining bias to said first means when said output approaches open circuit output impedance conditions.
Claim 2
Dependent Claim
221 words
A voltage controlled resistor circuit, comprising: an operational transconductance amplifier having an inverting input, a non-inverting input adpated to be coupled to a first source of supply voltage, a diode bias input, a bias input for receiving a gain control current, first and second power supply terminals adapted to be coupled to second and third supply voltages, respectively, and an output for exibiting a high output impedance when the gain control current is substantially zero, said output impedance decreasing as said gain control current increases, said operational transconductance amplifier having first and second linearizing diodes each having an anode coupled to said diode bias input, said first linearizing diode having a cathode coupled to said inverting input and said second linearizing diode having a cathode coupled to said non-inverting input; first means coupled to said output for providing a low impedance buffered output; first impedance means coupled to said diode bias input for producing current flow through said first and second linearizing diodes; second impedance means coupled to said low impedance buffered output for providing feedback to said inverting input and for supplying and controlling bias current to said first linearizing diode; and third impedance means coupled between said output and said diode bias input for maintaining bias to said first means when said output approaches open circuit output impedance conditions.
Claim 3
Dependent Claim
90 words
A voltage controlled resistor circuit according to claim 1 wherein said first means comprises: a first transistor having a base coupled to said output, a collector adapted to be coupled to said second supply voltage and having an emitter; and a second transistor having a base coupled to the emitter of said first transistor, a collector adapted to be coupled to said second supply voltage and an emitter adapted to be coupled to said third supply voltage, said low impedance buffered output appearing at the emitter of said second transistor.
Claim 4
Dependent Claim
18 words
A voltage controlled resistor circuit according to claim 2 wherein said first impedance means is a first resistor.
Claim 5
Dependent Claim
18 words
A voltage controlled resistor circuit according to claim 3 wherein said second impedance means is a second resistor.
Claim 6
Dependent Claim
17 words
A voltage controlled resistor according to claim 4 wherein said third impedance means is a third resistor.
Claim 7
Dependent Claim
19 words
A voltage controlled resistor according to claim 5 wherein said first resistor is substantially larger than said second resistor.
Claim 8
Dependent Claim
29 words
A voltage controlled resistor according to claim 6 further including a gain stage having an input coupled to the output of said operational transconductance amplifier and having an output.
Claim 9
Dependent Claim
24 words
A voltage controlled resistor according to claim 7 further including means coupled to the output of said gain stage for controlling said gain current.
Claim 10
Dependent Claim
26 words
A voltage controlled resistor according to claim 8 further including a fourth resistor coupled between the emitter of said second transistor and said third supply voltage.
Claim 11
Dependent Claim
135 words
A voltage controlled resistor circuit, comprising: an operational transconductance amplifier having an inverting input, a non-inverting input adapted to be coupled to a first source of supply voltage, bias input for receiving a gain control current, first and second power supply terminals adapted to be coupled to second and third supply voltages, respectively, and an output for exibiting a high output impedance when the gain control current is substantially zero, said output impedance drecreasing as said gain control current increases, comprising: first means coupled to said output for providing a low impedance buffered output; second impedance means coupled to said low impedance buffered output for providing feedback to said inverting input; and third impedance means coupled to said output for maintaining bias to said first means when said output approaches open circuit output impedance conditions.
Claim 12
Dependent Claim
135 words
A voltage controlled resistor circuit, comprising: an operational transconductance amplifier having an inverting input, a non-inverting input adapted to be coupled to a first source of supply voltage, bias input for receiving a gain control current, first and second power supply terminals adapted to be coupled to second and third supply voltages, respectively, and an output for exibiting a high output impedance when the gain control current is substantially zero, said output impedance drecreasing as said gain control current increases, comprising: first means coupled to said output for providing a low impedance buffered output; second impedance means coupled to said low impedance buffered output for providing feedback to said inverting input; and third impedance means coupled to said output for maintaining bias to said first means when said output approaches open circuit output impedance conditions.
Claim 13
Dependent Claim
79 words
A voltage controlled resistor circuit according to claim 10 further comprising: at least first and second diodes for linearizing the input of said operational transconductance amplifier, said first diode having a cathode coupled to said inverting input and said second diode having a cathode coupled to said non-inverting input, the anodes of said first and second diodes adapted to be coupled to a bias voltage source; and current limiting means coupled between said anodes and said bias voltage source.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-07-11 | 1987-01-10 | 1987-07-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-07-11 | 1991-01-10 | 1991-07-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-07-11 | 1995-01-10 | 1995-07-12 | $7700.00 | Window Closed / Lapsed |