Patent US4707431A successfully refreshed from Google Patents.
Patent US4392149A successfully refreshed from Google Patents.
US4392149A
Expired / Lapsed
US
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Bipolar transistor
Assignee: International Business Machines Corp
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Filing: 1981-06-15
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Granted: 1983-07-05
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Expires: 2001-06-15
Abstract
Abstract Disclosed is a self-aligned process for providing an improved bipolar transistor structure. The process includes the chemically etching of an intermediate insulating layer to undercut another top layer of a different insulating material in a self-aligned emitter process wherein the spacing of the emitter contact to the polysilicon base contact is reduced to a magnitude of approximately 0.2 to 0.3 micrometers. In addition, in the process an emitter plug is formed to block the emitter region from the heavy P+ ion dose implant of the extrinsic base.
Inventors
- 👤 Cheng T. Horng
- 👤 Robert O. Schwenker
- 👤 Paul J. Tsang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 16:00
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/051; H10D10/40; H10D10/441; H10D62/00; H10D62/10; H10D62/13; H10D62/133; H10D84/00; H10D84/01; H10D84/0112; H10D84/02; H10D84/03; H10D84/038; H10P; H10P76/00; H10P76/40; H10P76/405; H10P76/408; H10P76/4085
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
447 words
A planar self-aligned vertical bipolar transistor structure (FIG. 23), said structure comprising: a monolithic silicon substrate (1); a shallow depth silicon epitaxial layer having a substantially flat exposed top surface, said epitaxial layer having a thickness of approximately 2 micrometers; a shallow depth emitter region (FIG. 23, 12) formed in said expitaxial layer, said emitter region having an exposed essentially planar surface, said exposed planar surface of said emitter region being co-planar with said substantially flat exposed top surface of said epitaxial layer, said emitter region having a depth of approximately 200 nanometers; an intrinsic base region (FIG. 23, 19) formed in said epitaxial layer beneath said emitter region to provide an emitter-base junction, said emitter-base junction being substantially flat and having a predetermined area, said intrinsic base region having a depth measured from beneath said emitter-base junction of approximately 200 nanometers; an extrinsic base region (FIG. 23, 17) formed in said epitaxial layer, said extrinsic base laterally surrounding said emitter, said intrinsic base and emitter-base said junction; a collector region (FIG, 23, 4) formed in said epitaxial layer beneath said intrinsic base region to provide a base-collector junction, said base-collector junction being substantially flat and having an area essentially equal to said emitter-base junction; a subcollector region (FIG. 23, 3) contained in said monolithic silicon substrate beneath said collector and having a lateral extension in a first direction; a collector reach-through region (FIG. 23, 9) laterally displaced in said first direction from said vertical bipolar transistor, said collector reach-through region extending from said substantially flat exposed top surface of said epitaxial layer to said lateral extension of said subcollector region; an insulator region (FIG. 23, 6) positioned between said vertical bipolar transistor and said collector reach-through region, said insulator region having an upper essentially planar surface, said upper planar surface of said insulator means being essentially co-planar with substantially said flat exposed top surface of said epitaxial layer, said insulator region extending into said subcollector region and electrically isolating said extrinsic base region from said collector reach-through region; an extrinsic base polysilicon extension region (FIG. 23, 18) contained on said substantially flat exposed top surface of said epitaxial layer and making intimate physical contact with said extrinsic base region (FIG. 23, 17) formed in said epitaxial layer, said extrinsic base polysilicon extension region having a thickness of 200 to 300 nanometers; an emitter contact making intimate contact with said emitter region (FIG. 23, 12); and a thin layer of insulating material consisting of silicon dioxide and silicon nitride and having a thickness of approximately 0.2 to 0.3 micrometers, said thin layer of insulating material being positioned between said emitter contact and said extrinsic base polysilicon contact.
Claim 2
Dependent Claim
447 words
A planar self-aligned vertical bipolar transistor structure (FIG. 23), said structure comprising: a monolithic silicon substrate (1); a shallow depth silicon epitaxial layer having a substantially flat exposed top surface, said epitaxial layer having a thickness of approximately 2 micrometers; a shallow depth emitter region (FIG. 23, 12) formed in said expitaxial layer, said emitter region having an exposed essentially planar surface, said exposed planar surface of said emitter region being co-planar with said substantially flat exposed top surface of said epitaxial layer, said emitter region having a depth of approximately 200 nanometers; an intrinsic base region (FIG. 23, 19) formed in said epitaxial layer beneath said emitter region to provide an emitter-base junction, said emitter-base junction being substantially flat and having a predetermined area, said intrinsic base region having a depth measured from beneath said emitter-base junction of approximately 200 nanometers; an extrinsic base region (FIG. 23, 17) formed in said epitaxial layer, said extrinsic base laterally surrounding said emitter, said intrinsic base and emitter-base said junction; a collector region (FIG, 23, 4) formed in said epitaxial layer beneath said intrinsic base region to provide a base-collector junction, said base-collector junction being substantially flat and having an area essentially equal to said emitter-base junction; a subcollector region (FIG. 23, 3) contained in said monolithic silicon substrate beneath said collector and having a lateral extension in a first direction; a collector reach-through region (FIG. 23, 9) laterally displaced in said first direction from said vertical bipolar transistor, said collector reach-through region extending from said substantially flat exposed top surface of said epitaxial layer to said lateral extension of said subcollector region; an insulator region (FIG. 23, 6) positioned between said vertical bipolar transistor and said collector reach-through region, said insulator region having an upper essentially planar surface, said upper planar surface of said insulator means being essentially co-planar with substantially said flat exposed top surface of said epitaxial layer, said insulator region extending into said subcollector region and electrically isolating said extrinsic base region from said collector reach-through region; an extrinsic base polysilicon extension region (FIG. 23, 18) contained on said substantially flat exposed top surface of said epitaxial layer and making intimate physical contact with said extrinsic base region (FIG. 23, 17) formed in said epitaxial layer, said extrinsic base polysilicon extension region having a thickness of 200 to 300 nanometers; an emitter contact making intimate contact with said emitter region (FIG. 23, 12); and a thin layer of insulating material consisting of silicon dioxide and silicon nitride and having a thickness of approximately 0.2 to 0.3 micrometers, said thin layer of insulating material being positioned between said emitter contact and said extrinsic base polysilicon contact.
References Cited (Backward Citations)
US4236294A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-07-04 | 1987-01-03 | 1987-07-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-07-04 | 1991-01-03 | 1991-07-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-07-04 | 1995-01-03 | 1995-07-05 | $7700.00 | Window Closed / Lapsed |