Rotating register utilizing field effect transistors

Claim 2

A storage register comprising: an input means; an output means; a plurality of pairs of field effect transistor means and a plurality of pairs of clocking means arranged in a closed circuit loop having a first clocking means of a clocking means pair connected between the first and second field effect transistor means of a field effect transistor means pair, and having a second clocking means of the clocking means pair connected between each pair of field effect transistor means and having said input means connected between said first clocking means and said second field effect transistor means and having said output connected between said second field effect transistor means and said second clocking means.

Claim 3

A storage register according to claim 1, wherein said field effect transistor means includes an inverter.

Claim 4

A storage register according to claim 2, wherein said pairs of clocking means include first and second clock signals wherein the first clock signal becomes inactive before the second clock signal becomes active and the second clock signal becomes inactive before the first clock signal becomes active.

Claim 5

A storage register according to claim 3, wherein said input means includes a switching device.

Claim 6

A storage register according to claim 4, wherein said output means includes a switching device.

Claim 7

A rotating storage register for simultaneously storing a plurality of digital data words, each digital data word including a plurality of binary bits, said register comprising: a plurality of loops in parallel, each loop including a plurality of storage elements connected in series to form the loop, each storage element including a first and second field effect transistor means, each transistor means including a transistor input and a transistor output, and a first and second clocking means, each clocking means including a clocking input and a clocking output, arranged having the first field effect transistor means input connected to a serially preceeding storage element in the loop, the first field effect transistor means output connected to the first clocking means, the first clocking means output connected to the second field effect transistor means input, the second field effect transistor means output connected to the second clocking means input, the second clocking output connected to a next serially successive storage element in the loop; a plurality of data input lines connected to selected field effect transistor means inputs; and a plurality of data output lines connected to selected field effect transistor means outputs.

Claim 8

A rotating storage register for simultaneously storing a plurality of digital data words, each digital data word including a plurality of binary bits, said register comprising: a plurality of loops in parallel, each loop including a plurality of storage elements connected in series to form the loop, each storage element including a first and second field effect transistor means, each transistor means including a transistor input and a transistor output, and a first and second clocking means, each clocking means including a clocking input and a clocking output, arranged having the first field effect transistor means input connected to a serially preceeding storage element in the loop, the first field effect transistor means output connected to the first clocking means, the first clocking means output connected to the second field effect transistor means input, the second field effect transistor means output connected to the second clocking means input, the second clocking output connected to a next serially successive storage element in the loop; a plurality of data input lines connected to selected field effect transistor means inputs; and a plurality of data output lines connected to selected field effect transistor means outputs.

Claim 9

A rotating storage register according to claim 6, wherein said storage elements store a single bit of data.

Claim 10

A rotating storage register according to claim 7, wherein said data input lines includes an input switch.

Claim 11

A rotating storage register according to claim 8, wherein said data output lines include an output switch.

Claim 12

A rotating register according to claim 9, wherein first and second clocking means each include a first and second clocking switch, respectively, where the first and second clock switches are activated by a first and second clocking signals, respectively, said first clocking signal being active when said second clocking signal is inactive and said second clocking signal being active when said first clocking signal is inactive.

Claim 13

A rotating storage register according to claim 10, wherein the number of loops in parallel correspond to the number of binary bits in the digital data word.

Claim 14

A rotating storage register according to claim 11, wherein the number of storage elements in each loop correspond to the number of data words.

Claim 15

A rotating storage register according to claim 12, wherein said register is integrated monolithically on a single semiconductor substrate.

Claim 16

A rotating storage register according to claim 13, wherein said first and second clocking signals have frequencies in excess of 1 MHz.

Claim 17

A rotating storage register for simultaneously storing a plurality of digital data words, each digital data word including a plurality of binary bits, said register comprising: a plurality of loops in parallel, each loop including a plurality of pairs of field effect transistor means, each field effect transistor means including a field effect transistor means input and a field effect transistor means output, and a plurality of pairs of clocking means, each clocking means including a clocking input and a clocking means output, the plurality of field effect transistor means and clocking means connected in series having the first field effect transistor means output of a first position field effect transistor means pair connected to the first clocking means input of a successively positioned first clocking means pair, the first clocking means output of the first clocking means pair connected to the second field effect transistor means input of the first position field effect transistor means pair, the second field effect transistor means output of the first position field effect transistor means pair connected to the second clocking means input of the successively positioned first clocking means pair, the second clocking means output of the first clocking means pair connected to the first field effect transistor means input of a next successively positioned field effect transistor means pair and interconnected with the next successively positioned clocking means pair, and having the second clocking means output of the last clocking means pair connected to the first field effect transistor means input of the first positioned field effect transistor means pair to complete the loop; a plurality of data input lines connected to selected field effect transistor means inputs; and a plurality of data output lines connected to selected field effect transistor means outputs.

Claim 18

A rotating storage register for simultaneously storing a plurality of digital data words, each digital data word including a plurality of binary bits, said register comprising: a plurality of loops in parallel, each loop including a plurality of pairs of field effect transistor means, each field effect transistor means including a field effect transistor means input and a field effect transistor means output, and a plurality of pairs of clocking means, each clocking means including a clocking input and a clocking means output, the plurality of field effect transistor means and clocking means connected in series having the first field effect transistor means output of a first position field effect transistor means pair connected to the first clocking means input of a successively positioned first clocking means pair, the first clocking means output of the first clocking means pair connected to the second field effect transistor means input of the first position field effect transistor means pair, the second field effect transistor means output of the first position field effect transistor means pair connected to the second clocking means input of the successively positioned first clocking means pair, the second clocking means output of the first clocking means pair connected to the first field effect transistor means input of a next successively positioned field effect transistor means pair and interconnected with the next successively positioned clocking means pair, and having the second clocking means output of the last clocking means pair connected to the first field effect transistor means input of the first positioned field effect transistor means pair to complete the loop; a plurality of data input lines connected to selected field effect transistor means inputs; and a plurality of data output lines connected to selected field effect transistor means outputs.

Claim 19

A rotating storage register according to claim 15, wherein each of said data input lines includes a data input switch device.

Claim 20

A rotating storage register according to claim 16, wherein each of said data output lines includes a data output switching device.

Claim 21

A rotating storage register according to claim 17, wherein said first and second clocking means of said clocking means pair are activated by a first and second clocking signal, said first clocking signal being active when said second clocking signal is inactive and said second clocking signal being active when said first clocking is inactive.