Patent US4390769A successfully refreshed from Google Patents.
US4390769A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Induction heating apparatus providing smooth power control
Assignee: General Electric Co
•
Filing: 1980-05-29
•
Granted: 1983-06-28
•
Expires: 2000-05-29
Abstract
Abstract An improved induction heating apparatus comprises a full bridge inverter with each inverter leg fabricated of first and second serially coupled field effect transistors. A control apparatus coupled to the gate of each field effect transistor of each leg alternately renders the first and second field effect transistors of each inverter leg conductive. By varying the phase delay between initiation of alternate conduction of the field effect transistors of one inverter leg and subsequent initiation of alternate conduction of the field effect transistors of the other inverter legs in response to operator commands, smooth induction heating apparatus power control is achieved.
Inventors
- 👤 Robert L. Steigerwald
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 16:54
CPC Classifications
H; H05; H05B; H05B6/00; H05B6/02; H05B6/06; H05B6/062
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
677 words
An improved induction heating apparatus providing smooth power control comprising: a direct current power supply; a full bridge inverter having first and second legs, each inverter leg comprised of first and second gate turn-on switching means serially coupled across the output of said direct current power supply, each of said first and second gate turn-off switching means of each inverter leg comprising a field transistor and a diode coupled in the reverse power supply voltage direction across the drain-to-source portion of said field effect transistor; a resonant induction drive coil load circuit coupled between the junctions of the switching means of said first and second inverter legs, respectively; and a control apparatus coupled to each of said switching means of said first and second inverter legs for rendering said first and second switching means of each said inverter leg conductive at alternate intervals, said control apparatus controllably delaying initiation of alternate conduction of the switching means of said second inverter leg after initiation of alternate conduction of the switching means of said first inverter leg in accordance with the magnitude of an operator-varied voltage, thereby permitting smooth variation of inverter output power between 0 to 100 percent of maximum output power, said control apparatus comprising an astable multivibrator clock means for generating an output signal at uniform periodic intervals, first circuit means having a first input coupled to the junction between switching means of said first inverter leg and having a second input coupled to said clock means, said first circuit means coupled at its first and second outputs to a separate one of said first and second switching means of said first inverter leg, respectively, and alternately rendering one of said first and second switching means of said first inverter leg conductive in response to said clock means output signal, said first circuit means comprising a toggle flip-flop having an input coupled to said clock means and producing an output voltage which alternately changes in amplitude between a first and second level in response to said clock means output clock signal, an overlap control circuit having an input coupled to the junction between switching devices of said first inverter leg and producing an output voltage which changes in amplitude from a first to a second level in response to the voltage at its input, a logic circuit coupled at its first input to said toggle flip-flop and coupled at its second input to said overlap control circuit, said logic circuit producing a first output voltage whose amplitude changes from a first to a second level in accordance with a first predetermined relationship between voltages at it first and second inputs and producing a second output voltage whose amplitude changes from a first to a second level in accordance with a second predetermined relationship between voltages at its first and second input and gate drive circuit means coupled at its first and second input to said logic circuit means and coupled at each of its first and second output to a separate one of said first and second switching means, respectively, of said first inverter leg, said gate drive circuit supply said first and second switching means with gate drive voltage in accordance with the amplitude of a separate one of said logic circuit first and second output voltages, respectively, delay circuit means having an input coupled to said clock means, said delay circuit means generating an output signal after an interval following receipt of said clock means output signal, said interval being variable in duration in accordance with said operator-varied voltage, and second circuit means having a first input coupled to the junction between switching means of said second inverter leg and having a second input coupled to said delay circuit means, said second circuit means coupled at its first and second outputs to a separate one of said first and second switching means of said second inverter leg, respectively, and alternately rendering one of said first and second switching means of said second inverter leg conductive in response to said delay circuit means output signal.
Claim 2
Dependent Claim
677 words
An improved induction heating apparatus providing smooth power control comprising: a direct current power supply; a full bridge inverter having first and second legs, each inverter leg comprised of first and second gate turn-on switching means serially coupled across the output of said direct current power supply, each of said first and second gate turn-off switching means of each inverter leg comprising a field transistor and a diode coupled in the reverse power supply voltage direction across the drain-to-source portion of said field effect transistor; a resonant induction drive coil load circuit coupled between the junctions of the switching means of said first and second inverter legs, respectively; and a control apparatus coupled to each of said switching means of said first and second inverter legs for rendering said first and second switching means of each said inverter leg conductive at alternate intervals, said control apparatus controllably delaying initiation of alternate conduction of the switching means of said second inverter leg after initiation of alternate conduction of the switching means of said first inverter leg in accordance with the magnitude of an operator-varied voltage, thereby permitting smooth variation of inverter output power between 0 to 100 percent of maximum output power, said control apparatus comprising an astable multivibrator clock means for generating an output signal at uniform periodic intervals, first circuit means having a first input coupled to the junction between switching means of said first inverter leg and having a second input coupled to said clock means, said first circuit means coupled at its first and second outputs to a separate one of said first and second switching means of said first inverter leg, respectively, and alternately rendering one of said first and second switching means of said first inverter leg conductive in response to said clock means output signal, said first circuit means comprising a toggle flip-flop having an input coupled to said clock means and producing an output voltage which alternately changes in amplitude between a first and second level in response to said clock means output clock signal, an overlap control circuit having an input coupled to the junction between switching devices of said first inverter leg and producing an output voltage which changes in amplitude from a first to a second level in response to the voltage at its input, a logic circuit coupled at its first input to said toggle flip-flop and coupled at its second input to said overlap control circuit, said logic circuit producing a first output voltage whose amplitude changes from a first to a second level in accordance with a first predetermined relationship between voltages at it first and second inputs and producing a second output voltage whose amplitude changes from a first to a second level in accordance with a second predetermined relationship between voltages at its first and second input and gate drive circuit means coupled at its first and second input to said logic circuit means and coupled at each of its first and second output to a separate one of said first and second switching means, respectively, of said first inverter leg, said gate drive circuit supply said first and second switching means with gate drive voltage in accordance with the amplitude of a separate one of said logic circuit first and second output voltages, respectively, delay circuit means having an input coupled to said clock means, said delay circuit means generating an output signal after an interval following receipt of said clock means output signal, said interval being variable in duration in accordance with said operator-varied voltage, and second circuit means having a first input coupled to the junction between switching means of said second inverter leg and having a second input coupled to said delay circuit means, said second circuit means coupled at its first and second outputs to a separate one of said first and second switching means of said second inverter leg, respectively, and alternately rendering one of said first and second switching means of said second inverter leg conductive in response to said delay circuit means output signal.
Claim 3
Dependent Claim
246 words
The invention according to claim 1 wherein said gate drive circuit means comprises: a low voltage power supply; a first transformer having a primary winding and secondary winding, said secondary winding coupled to said first switching means of said first inverter leg; a first transistor having a base coupled to a first output of said logic circuit and having a collector and emitter, the collector-to-emitter portion of said first transistor coupled in series with said primary of said first transformer between said low voltage power supply and circuit ground, said first transistor, when rendered conductive, rendering said first switching means of said first inverter leg conductive; means coupled across said primary of said first transformer for providing a completed path for decreasing transformer currents during intervals when said first transistor is nonconductive; a second transformer having a primary winding and having a secondary winding coupled to said second switching means of said first inverter leg; a second transistor having a base coupled to a second output of said logic circuit and having a collector and emitter, the collector-to-emitter portion of said second transistor coupled in series with said primary of said second transformer between said low voltage power supply and circuit ground, said second transistor, when rendered conductive, rendering said second switching means of said first inverter leg conductive; and means coupled across the primary of said second transformer for providing a completed path for decreasing transformer currents during intervals when said second transistor is nonconductive.
Claim 4
Dependent Claim
137 words
The invention according to claim 1 wherein said logic circuit comprises: a first two input NOR gate having a first input coupled to said overlap control circuit, a second input coupled to said toggle flip-flop and having an output coupled to the first input of said gate drive circuit means; a second two input NOR gate having first and second inputs and an output, said output coupled to said second input of said gate drive circuit means; a first NOT gate coupled at its input to the output of said overlap control circuit and coupled at its output to the first input of said second NOR gate; and a second NOT gate coupled at its input to the output of said toggle flip-flop and coupled at its output to the second input of said second NOR gate.
Claim 5
Dependent Claim
548 words
An improved induction heating apparatus providing smooth power control comprising: a direct current power supply; a full bridge inverter having first and second legs, each inverter leg comprised of first and second gate turn-on switching means serially coupled across the output of said direct current power supply, each of said first and second gate turn-off switching means of each inverter leg comprises a field effect transistor and a diode coupled in the reverse power supply voltage direction across the drain-to-source portion of said field effect transistor; a resonant induction drive coil load circuit coupled between the junctions of the switching means of said first and second inverter legs, respectively; and a control apparatus coupled to each of said switching means of said first and second inverter legs for rendering said first and second switching means of each said inverter leg conductive at alternate intervals, said control apparatus controllably delaying initiation of alternate conduction of the switching means of said second inverter leg after initiation of alternate conduction of the switching means of said first inverter leg in accordance with the magnitude of an operator-varied voltage, thereby permitting smooth variation of inverter output power between 0 to 100 percent of maximum output power, said control apparatus comprising an astable multivibrator clock means for generating an output signal at uniform periodic intervals, first circuit means having a first input coupled to the junction between switching means of said first inverter leg and having a second input coupled to said clock means, said first circuit means coupled at its first and second outputs to a separate one of said first and second switching means of said first inverter leg, respectively, and alternately rendering one of said first and second switching means of said first inverter leg conductive in response to said clock means output signal, delay circuit means having an input coupled to said clock means, said delay circuit means generating an output signal after an interval following receipt of said clock means output signal, said interval being variable in duration in accordance with said operator-varied voltage, said delay circuit means comprising a multivibrator circuit having an input coupled to said clock means, a pair of timing port inputs, and an output coupled to the second input of said second circuit means, said multivibrator producing an output signal after an interval following receipt of a clock signal from said clock means, said interval varying in duration in accordance with the voltage amplitude across said pair of timing port inputs, a capacitance coupled across said pair of timing port inputs of said multivibrator, and means coupled to said capacitance for varying the charge on said capacitance and thereby varying the voltage across said pair of timing port inputs of said multivibrator in accordance with said operator-varied voltage, and second circuit means having a first input coupled to the junction between switching means of said second inverter leg and having a second input coupled to said delay circuit means, said second circuit means coupled at its first and second outputs to a separate one of said first and second switching means of said second inverter leg, respectively, and alternately rendering one of said first and second switching means of said second inverter leg conductive in response to said delay circuit means output signal.
Claim 6
Dependent Claim
548 words
An improved induction heating apparatus providing smooth power control comprising: a direct current power supply; a full bridge inverter having first and second legs, each inverter leg comprised of first and second gate turn-on switching means serially coupled across the output of said direct current power supply, each of said first and second gate turn-off switching means of each inverter leg comprises a field effect transistor and a diode coupled in the reverse power supply voltage direction across the drain-to-source portion of said field effect transistor; a resonant induction drive coil load circuit coupled between the junctions of the switching means of said first and second inverter legs, respectively; and a control apparatus coupled to each of said switching means of said first and second inverter legs for rendering said first and second switching means of each said inverter leg conductive at alternate intervals, said control apparatus controllably delaying initiation of alternate conduction of the switching means of said second inverter leg after initiation of alternate conduction of the switching means of said first inverter leg in accordance with the magnitude of an operator-varied voltage, thereby permitting smooth variation of inverter output power between 0 to 100 percent of maximum output power, said control apparatus comprising an astable multivibrator clock means for generating an output signal at uniform periodic intervals, first circuit means having a first input coupled to the junction between switching means of said first inverter leg and having a second input coupled to said clock means, said first circuit means coupled at its first and second outputs to a separate one of said first and second switching means of said first inverter leg, respectively, and alternately rendering one of said first and second switching means of said first inverter leg conductive in response to said clock means output signal, delay circuit means having an input coupled to said clock means, said delay circuit means generating an output signal after an interval following receipt of said clock means output signal, said interval being variable in duration in accordance with said operator-varied voltage, said delay circuit means comprising a multivibrator circuit having an input coupled to said clock means, a pair of timing port inputs, and an output coupled to the second input of said second circuit means, said multivibrator producing an output signal after an interval following receipt of a clock signal from said clock means, said interval varying in duration in accordance with the voltage amplitude across said pair of timing port inputs, a capacitance coupled across said pair of timing port inputs of said multivibrator, and means coupled to said capacitance for varying the charge on said capacitance and thereby varying the voltage across said pair of timing port inputs of said multivibrator in accordance with said operator-varied voltage, and second circuit means having a first input coupled to the junction between switching means of said second inverter leg and having a second input coupled to said delay circuit means, said second circuit means coupled at its first and second outputs to a separate one of said first and second switching means of said second inverter leg, respectively, and alternately rendering one of said first and second switching means of said second inverter leg conductive in response to said delay circuit means output signal.
Claim 7
Dependent Claim
106 words
The invention according to claim 4 wherein said means to vary the charge on said capacitance comprises: a low voltage power supply; a first transistor having a base, collector and emitter, the collector-to-emitter portion of said first transistor being coupled between said capacitance and said low voltage power supply; and a second transistor having a base, collector and emitter, the collector-to-emitter portion of said second transistor being coupled between the base of said first transistor and circuit ground, said second transistor controlling the current carried by said first transistor and thereby controlling the charge on said capacitance in accordance with the magnitude of said operator-varied voltage.
Claim 8
Dependent Claim
658 words
An improved induction heating apparatus providing smooth power control comprising: a direct current power supply; a full bridge inverter having first and second legs, each inverter leg comprised of first and second gate turn-on switching means serially coupled across the output of said direct current power supply, each of said first and second gate turn-off switching means of each inverter leg comprising a field effect transistor, and a diode coupled in the reverse power supply voltage direction across the dtain-to-source portion of said field effect transistor; a resonant induction drive coil load circuit coupled between the junctions of the switching means of said first and second inverter legs, respectively; and a control apparatus coupled to each of said switching means of said first and second inverter legs for rendering said first and second switching means of each said inverter leg conductive at alternate intervals, said control apparatus controllably delaying initiation of alternate conduction of the switching means of said second inverter leg after initiation of alternate conduction of the switching means of said first inverter leg in accordance with the magnitude of an operator-varied voltage, thereby permitting smooth variation of inverter output power between 0 to 100 percent of maximum output power, said control apparatus comprising an astable multivibrator clock means for generating an output signal at uniform periodic intervals, first circuit means having a first input coupled to the junction between switching means of said first inverter leg and having a second input coupled to said clock means, said first circuit means coupled at its first and second outputs to a separate one of said first and second switching means of said first inverter leg, respectively, and alternately rendering one of said first and second switching means of said first inverter leg conductive in response to said clock means output signal, delay circuit means having an input coupled to said clock means, said delay circuit means generating an output signal after an interval following receipt of said clock means output signal, said interval being variable in duration in accordance with said operator-varied voltage and second circuit means having a first input coupled to the junction between switching means of said second inverter leg and having a second input coupled to said delay circuit means, said second circuit means coupled at its first and second outputs to a separate one of said first and second switching means of said second inverter leg, respectively, and alternately rendering one of said first and second switching means of said second inverter leg conductive in response to said delay circuit means output signal, said second circuit means comprising toggle flip-flop means having an input coupled to said delay circuit means and producing an output voltage which alternately changes in amplitude between a first level and a second level in response to the output signal of said delay circuit means, an overlap control circuit having an input coupled to the junction between switching devices of said second inverter leg and producing an output voltage which changes in amplitude from a first to a second level in response to the amplitude of voltage at its input, a logic circuit coupled at its first input to said toggle flip-flop means and coupled at its second input to said overlap control circuit, said logic circuit producing a first output voltage whose amplitude changes from a first level to a second level in accordance with a first predetermined relationship between voltages at its first and second inputs and producing a second output voltage whose amplitude changes from a first level to a second level in accordance with a second predetermined relationship between voltages at its first and second inputs, and gate drive circuit means coupled at its first and second inputs to said logic circuit means and coupled at its first and second outputs to a separate one of said second and first switching means of said second inverter leg, respectively, for supplying gate drive voltage thereto.
Claim 9
Dependent Claim
658 words
An improved induction heating apparatus providing smooth power control comprising: a direct current power supply; a full bridge inverter having first and second legs, each inverter leg comprised of first and second gate turn-on switching means serially coupled across the output of said direct current power supply, each of said first and second gate turn-off switching means of each inverter leg comprising a field effect transistor, and a diode coupled in the reverse power supply voltage direction across the dtain-to-source portion of said field effect transistor; a resonant induction drive coil load circuit coupled between the junctions of the switching means of said first and second inverter legs, respectively; and a control apparatus coupled to each of said switching means of said first and second inverter legs for rendering said first and second switching means of each said inverter leg conductive at alternate intervals, said control apparatus controllably delaying initiation of alternate conduction of the switching means of said second inverter leg after initiation of alternate conduction of the switching means of said first inverter leg in accordance with the magnitude of an operator-varied voltage, thereby permitting smooth variation of inverter output power between 0 to 100 percent of maximum output power, said control apparatus comprising an astable multivibrator clock means for generating an output signal at uniform periodic intervals, first circuit means having a first input coupled to the junction between switching means of said first inverter leg and having a second input coupled to said clock means, said first circuit means coupled at its first and second outputs to a separate one of said first and second switching means of said first inverter leg, respectively, and alternately rendering one of said first and second switching means of said first inverter leg conductive in response to said clock means output signal, delay circuit means having an input coupled to said clock means, said delay circuit means generating an output signal after an interval following receipt of said clock means output signal, said interval being variable in duration in accordance with said operator-varied voltage and second circuit means having a first input coupled to the junction between switching means of said second inverter leg and having a second input coupled to said delay circuit means, said second circuit means coupled at its first and second outputs to a separate one of said first and second switching means of said second inverter leg, respectively, and alternately rendering one of said first and second switching means of said second inverter leg conductive in response to said delay circuit means output signal, said second circuit means comprising toggle flip-flop means having an input coupled to said delay circuit means and producing an output voltage which alternately changes in amplitude between a first level and a second level in response to the output signal of said delay circuit means, an overlap control circuit having an input coupled to the junction between switching devices of said second inverter leg and producing an output voltage which changes in amplitude from a first to a second level in response to the amplitude of voltage at its input, a logic circuit coupled at its first input to said toggle flip-flop means and coupled at its second input to said overlap control circuit, said logic circuit producing a first output voltage whose amplitude changes from a first level to a second level in accordance with a first predetermined relationship between voltages at its first and second inputs and producing a second output voltage whose amplitude changes from a first level to a second level in accordance with a second predetermined relationship between voltages at its first and second inputs, and gate drive circuit means coupled at its first and second inputs to said logic circuit means and coupled at its first and second outputs to a separate one of said second and first switching means of said second inverter leg, respectively, for supplying gate drive voltage thereto.
Claim 10
Dependent Claim
155 words
The invention according to claim 6 wherein said gate drive circuit means comprises: a low voltage power supply; a first transformer having a primary winding and secondary winding, said secondary winding coupled to said first switching means of said second inverter leg; a first transistor having a base coupled to a first output of said logic circuit and having a collector and emitter, the collector-to-emitter portion of said first transistor coupled in series with said primary of said first transformer between said low voltage power supply and circuit ground, said first transistor, when rendered conductive, rendering said first switching means of said second inverter leg conductive; means coupled across said primary of said first transformer for providing a completed path for decreasing transformer currents during intervals when said first transistor is nonconductive; a second transformer having a primary winding and having a secondary winding coupled to said second switching means of said second inverter leg;
Claim 11
Dependent Claim
91 words
a second transistor having a base coupled to a second output of said logic circuit and having a collector and emitter, the collector-to-emitter portion of said second transistor coupled in series with said primary of said second transformer between said low voltage power supply and circuit ground, said second transistor, when rendered conductive, rendering said second switching means of said second inverter leg conductive, and means coupled across the primary of said second transformer for providing a completed path for decreasing transformer currents during intervals when said second transistor is nonconductive.
Claim 12
Dependent Claim
91 words
a second transistor having a base coupled to a second output of said logic circuit and having a collector and emitter, the collector-to-emitter portion of said second transistor coupled in series with said primary of said second transformer between said low voltage power supply and circuit ground, said second transistor, when rendered conductive, rendering said second switching means of said second inverter leg conductive, and means coupled across the primary of said second transformer for providing a completed path for decreasing transformer currents during intervals when said second transistor is nonconductive.
Claim 13
Dependent Claim
137 words
The invention according to claim 6 wherein said logic current comprises: a first two input NOR gate having its first input coupled to said overlap control circuit, its second input coupled to said toggle flip-flop and having an output coupled to the first input of said gate drive circuit means; a second two input NOR gate having first and second inputs and an output, said output coupled to said second input of said gate drive circuit means; a first NOT gate coupled at its input to the output of said overlap control circuit and coupled at its output to the first input of said second NOR gate; and a second NOT gate coupled at its input to the output of said toggle flip-flop and coupled at its output to the second input of said second NOR gate.
References Cited (Backward Citations)
US3466528A
Cited
US3898410A
Cited
US4085300A
Cited
US4115676A
Cited
US4211912A
Cited
US4201957A
Cited
US4241250A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-06-27 | 1986-12-27 | 1987-06-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-06-27 | 1990-12-27 | 1991-06-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-06-27 | 1994-12-27 | 1995-06-28 | $7700.00 | Window Closed / Lapsed |