Patent US4385395A successfully refreshed from Google Patents.
US4385395A
Expired / Lapsed
US
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Bit clock reproducing circuit
Assignee: Sony Corp
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Filing: 1981-04-15
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Granted: 1983-05-24
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Expires: 2001-04-15
Abstract
Abstract A bit clock reproducing circuit produces an output bit clock signal in response to an input clock signal but without reproducing jitter present in the input signal. A counter is supplied with a reference clock signal as a counting input, and the counter is periodically loaded, at a fixed time during each cycle of the input clock signal, with data which is a predetermined function of the state of the counter at such times.
Inventors
- 👤 Masato Tanaka
- 👤 Nobuhiko Watanabe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 14:10
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0331; G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
166 words
A bit clock reproducing circuit comprising: (a) a first input terminal for receiving input data; (b) a second input terminal for receiving a reference clock signal; (c) first circuit means connected with said first and second terminals and responsive to said input data and said reference clock signal for producing a control signal corresponding to the edge of said input data; (d) counter means connected to said first circuit means and responsive to said control signal for receiving initial data, said counter means being connected to said second input terminal and responsive to said reference clock signal for producing a counting output signal; (e) second circuit means connected to said counter means and responsive to said counting output signal for generating an output data signal which is a predetermined function of said output counting signal, said output data signal being provided to said counter means as said initial data; and (f) an output terminal for manifesting a bit clock signal corresponding to said counting output signal.
Claim 2
Dependent Claim
166 words
A bit clock reproducing circuit comprising: (a) a first input terminal for receiving input data; (b) a second input terminal for receiving a reference clock signal; (c) first circuit means connected with said first and second terminals and responsive to said input data and said reference clock signal for producing a control signal corresponding to the edge of said input data; (d) counter means connected to said first circuit means and responsive to said control signal for receiving initial data, said counter means being connected to said second input terminal and responsive to said reference clock signal for producing a counting output signal; (e) second circuit means connected to said counter means and responsive to said counting output signal for generating an output data signal which is a predetermined function of said output counting signal, said output data signal being provided to said counter means as said initial data; and (f) an output terminal for manifesting a bit clock signal corresponding to said counting output signal.
Claim 3
Dependent Claim
67 words
A bit clock reproducing circuit as claimed in claim 1, wherein said second circuit means is formed of a read only memory having address inputs of plural bits and memory outputs of plural bits, the counting output signals of said counter means being supplied to said address inputs of said read only memory, and the memory data corresponding thereto supplied to said counter means as initial values.
Claim 4
Dependent Claim
140 words
A bit clock signal reproducing circuit comprising, a first flip-flop, a second flip-flop connected to the output of said first flip-flop, an OR gate connected to the outputs of said first and second flip-flops, a counter connected to the output of said OR gate and producing a plurality of outputs, a ROM receiving said plurality of outputs of said counter and producing a plurality of outputs which are supplied to said counter, an input clock pulse source terminal connected to said first and second flip-flops and to said counter, a third flip-flop receiving, as an input, a signal from said counter, an input data terminal supplying inputs to said first and third flip-flops, and an output terminal connected to the output of said third flip-flop to produce said clock bit signal corresponding to the plurality of outputs of said counter.
Claim 5
Dependent Claim
140 words
A bit clock signal reproducing circuit comprising, a first flip-flop, a second flip-flop connected to the output of said first flip-flop, an OR gate connected to the outputs of said first and second flip-flops, a counter connected to the output of said OR gate and producing a plurality of outputs, a ROM receiving said plurality of outputs of said counter and producing a plurality of outputs which are supplied to said counter, an input clock pulse source terminal connected to said first and second flip-flops and to said counter, a third flip-flop receiving, as an input, a signal from said counter, an input data terminal supplying inputs to said first and third flip-flops, and an output terminal connected to the output of said third flip-flop to produce said clock bit signal corresponding to the plurality of outputs of said counter.
Claim 6
Dependent Claim
53 words
A bit clock signal reproducing circuit means according to claim 3 wherein said ROM has address inputs of plural bits and memory outputs of plural bits with the plurality outputs of said counter supplied to the address inputs of said ROM and said memory outputs of said ROM being supplied to said counter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-05-23 | 1986-11-22 | 1987-05-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-05-23 | 1990-11-22 | 1991-05-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-05-23 | 1994-11-22 | 1995-05-24 | $7700.00 | Window Closed / Lapsed |