Data shunting and recovering device

Claim 2

A data shunting and recovering device for use with an information system in which the execution of an instruction is carried out over a plurality of time cycles and in which said instruction execution is stopped upon generation of an interrupt, comprising: register means including a plurality of addressable registers for storing data; address means for specifying an address of one of said registers in order that data can be read out of and written therein; means for delaying the stopping of said instruction execution with a delay period of at least one of said time cycles upon generation of said interrupt to allow said instruction to be executed for at least one of said time cycles following generation of said interrupt; means operative when said register specified by said address means is to be written on execution of the instruction during said delay period for shunting and holding an address which has been specified by said address means and the data which is read out of said register, said shunting and holding being done prior to the writing of said register during said delay period; and means responsive to a signal indicating restoration of said register to restore said address held in said holding means into said address means and send said data held in said holding means to said register means thereby restoring said data into the register specified by said restored address so that said register is restored to the same state as that which existed prior to the writing of the register during said delay period.

Claim 3

A data shunting and recovering device for use with an information system in which the execution of an instruction is carried out over a plurality of time cycles and in which the instruction execution is stopped upon generation of an interrupt, comprising: a plurality of register means for storing data, each of said register means including a plurality of addressable registers; address means corresponding to each of said plurality of register means for specifying an address of one of said registers, in order that data can be read out of and written in said register means; means for delaying the stopping of said instruction execution with a delay period of at least one of said time cycles upon generation of said interrupt to allow said instruction to be executed for at least one of said time cycles following generation of said interrupt; means operative when said register specified by said address means is to be written on execution of the instruction during said delay period for shunting and holding an address which has been specified by said address means and the data which is read out of said register, said shunting and holding being done prior to the writing of said register during said delay period; means for indicating the register means which has been actually written during the delay period; and means responsive to an indication of said indicating means and to a signal indicating restoration of said register to restore said address held in said holding means into said address means and send said data held in said holding means to said register means thereby restoring said data into the register specified by said restored address so that said register is restored to the same state as that which existed prior to the writing of the register during said delay period.

Claim 4

A data shunting and recovering device for use with an information system in which the execution of an instruction is carried out over a plurality of time cycles and in which the instruction execution is stopped upon generation of an interrupt, comprising: a plurality of register means for storing data, each of said register means including a plurality of addressable registers; address means corresponding to each of said plurality of register means for specifying an address of one of said registers, in order that data can be read out of and written in said register means; means for delaying the stopping of said instruction execution with a delay period of at least one of said time cycles upon generation of said interrupt to allow said instruction to be executed for at least one of said time cycles following generation of said interrupt; means operative when said register specified by said address means is to be written on execution of the instruction during said delay period for shunting and holding an address which has been specified by said address means and the data which is read out of said register, said shunting and holding being done prior to the writing of said register during said delay period; means for indicating the register means which has been actually written during the delay period; and means responsive to an indication of said indicating means and to a signal indicating restoration of said register to restore said address held in said holding means into said address means and send said data held in said holding means to said register means thereby restoring said data into the register specified by said restored address so that said register is restored to the same state as that which existed prior to the writing of the register during said delay period.

Claim 5

A data shunting and recovering device according to claim 1, wherein said address means includes first address means for use in read and second address means for use in write, and said holding means is connected to said second address means.

Claim 6

A data shunting and recovering device according to claim 2, wherein said address means includes first address means for use in read and second address means for use in write, and said holding means is connected to said second address means.

Claim 7

A data shunting and recovering device for use with an information system in which the execution of an instruction is carried out over a plurality of time cycles and in which said instruction execution is stopped upon generation of an interrupt, comprising: register means including a plurality of addressable registers for storing data; address means for specifying an address of one of said registers in order that data can be read out of and written therein; means for writing said register during a predetermined stage of said instruction execution; means for delaying the stopping of said instruction execution with a delay period of at least one of said time cycles upon generation of said interrupt to allow said instruction to be executed for at least one of said time cycles following generation of said interrupt; shunting and holding means, operative during said delay period when said instruction execution is in said predetermined stage of instruction execution during which said register specified by said address means is written on execution of the instruction during said delay period, for shunting and holding an address which has been specified by said address means and the data which is read out of said register, said shunting and holding being done prior to the writing of said register during said delay period; and means responsive to a signal indicating restoration of said register to restore said address held in said holding means into said address means and send said data held in said holding means to said register means thereby restoring said data into the register specified by said restored address so that said register is restored to the same state as that which existed prior to the writing of the register during said delay period.

Claim 8

A data shunting and recovering device for use with an information system in which the execution of an instruction is carried out over a plurality of time cycles and in which said instruction execution is stopped upon generation of an interrupt, comprising: register means including a plurality of addressable registers for storing data; address means for specifying an address of one of said registers in order that data can be read out of and written therein; means for writing said register during a predetermined stage of said instruction execution; means for delaying the stopping of said instruction execution with a delay period of at least one of said time cycles upon generation of said interrupt to allow said instruction to be executed for at least one of said time cycles following generation of said interrupt; shunting and holding means, operative during said delay period when said instruction execution is in said predetermined stage of instruction execution during which said register specified by said address means is written on execution of the instruction during said delay period, for shunting and holding an address which has been specified by said address means and the data which is read out of said register, said shunting and holding being done prior to the writing of said register during said delay period; and means responsive to a signal indicating restoration of said register to restore said address held in said holding means into said address means and send said data held in said holding means to said register means thereby restoring said data into the register specified by said restored address so that said register is restored to the same state as that which existed prior to the writing of the register during said delay period.