Computer with a memory system for remapping a memory having two memory output buses for high resolution display with scrolling of the displayed characters

Claim 2

In a digital computer which includes a central processing unit (CPU), a random-access memory (RAM), an address bus interconnecting said CPU and RAM such that said CPU addresses locations in said RAM and a data bus interconnecting said CPU and RAM, said CPU for certain functions addressing predetermined locations in said RAM with a predetermined range of address signals, an improvement comprising: detection means for detecting said predetermined range of address signals, coupled to said address bus; register means for storing digital signals, coupled to said data bus, and; switching means for coupling said digital signals stored in said register means to said address bus when said detection means detects said predetermined range of said address signals; whereby data for said certain functions normally stored by said CPU in said predetermined locations may be stored elsewhere in said RAM, thereby enhancing the performance of said computer.

Claim 3

The improvement defined by claim 2 wherein said detection means detects all binary zeros.

Claim 4

The improvement defined by claim 1 wherein said switching means comprises a multiplexer controlled by said detection means for selecting said register means.

Claim 5

The improvement defined by claim 1 including a read-only memory coupled to said address bus and said data bus.

Claim 6

The improvement defined by claim 4 wherein said stored signals in said register means provide a pointer for locations in said RAM during a direct memory access transfer.

Claim 7

The improvement defined by claim 5 wherein said read-only memory in response to signals on said address bus provides instructions to said CPU causing it to increment address signals during said direct memory access transfer.

Claim 8

In a digital computer which includes a central processing unit (CPU), a random-access memory (RAM), an address bus having a first plurality and a second plurality of lines for coupling said CPU with said RAM, and a data bus interconnecting said CPU and RAM, said CPU for certain operations addressing predetermined locations in said RAM with address signals on said first plurality of lines by coupling a predetermined address on said second plurality of lines, an improvement comprising: register means for storing signals, coupled to said data bus; multiplexing means coupled to said second plurality of lines and said register means for selecting signals from one of said second plurality of lines and said register means; logic means coupled to said second plurality of lines and said multiplexing means for causing said multiplexing means to select signals from said register means when said CPU couples said predetermined address on said second plurality of lines; whereby said signals from said register means provide alternate locations in RAM for storage associated with said certain operations.

Claim 9

In a digital computer which includes a central processing unit (CPU), a random-access memory (RAM), an address bus having a first plurality and a second plurality of lines for coupling said CPU with said RAM, and a data bus interconnecting said CPU and RAM, said CPU for certain operations addressing predetermined locations in said RAM with address signals on said first plurality of lines by coupling a predetermined address on said second plurality of lines, an improvement comprising: register means for storing signals, coupled to said data bus; multiplexing means coupled to said second plurality of lines and said register means for selecting signals from one of said second plurality of lines and said register means; logic means coupled to said second plurality of lines and said multiplexing means for causing said multiplexing means to select signals from said register means when said CPU couples said predetermined address on said second plurality of lines; whereby said signals from said register means provide alternate locations in RAM for storage associated with said certain operations.

Claim 10

The improvement defined by claim 7 wherein said predetermined address is all binary zeros.

Claim 11

The improvement defined by claim 7 including a read-only memory coupled to said address bus and said data bus.

Claim 12

The improvement defined by claim 8 wherein said stored signal in said register means provides a pointer for locations in said RAM during a direct memory access transfer.

Claim 13

The improvement defined by claim 9 wherein said read-only memory in response to signals on said address bus provides instructions to said CPU causing it to increment address signals during said direct memory access transfer.

Claim 14

In a digital processor used in conjunction with a display, said processor including a data bus and an address bus, a memory comprising: a first plurality of memory devices for storing data, coupled to receive data from said data bus; a first memory output bus coupled to receive data from said first plurality of memory device; a second plurality of memory devices for storing data coupled to receive data from said data bus; a second memory output bus coupled to receive data from said second plurality of memory devices; addressing means coupled to said address bus for providing address signal for addressing said first and second plurality of memory devices; first switching means for selecting data from one of said first and second memory buses for coupling to said data bus, said first switching means coupled to said first and second memory bus and said data bus; second switching means for selecting data from said first and second memory buses for coupling to said display, said second switching means coupled to said first and second memory buses and said display; and, circuit means for coupling one of a selected said first and second memory buses to said addressing means such that data from said selected one of said buses provides addressing information for selecting subsequent locations in said memory devices when said data bus is receiving data from the other of said memory buses, whereby said memory provides data for a high resolution display and whereby some data stored in said memory is used for remapping locations in said memory.

Claim 15

In a digital processor used in conjunction with a display, said processor including a data bus and an address bus, a memory comprising: a first plurality of memory devices for storing data, coupled to receive data from said data bus; a first memory output bus coupled to receive data from said first plurality of memory device; a second plurality of memory devices for storing data coupled to receive data from said data bus; a second memory output bus coupled to receive data from said second plurality of memory devices; addressing means coupled to said address bus for providing address signal for addressing said first and second plurality of memory devices; first switching means for selecting data from one of said first and second memory buses for coupling to said data bus, said first switching means coupled to said first and second memory bus and said data bus; second switching means for selecting data from said first and second memory buses for coupling to said display, said second switching means coupled to said first and second memory buses and said display; and, circuit means for coupling one of a selected said first and second memory buses to said addressing means such that data from said selected one of said buses provides addressing information for selecting subsequent locations in said memory devices when said data bus is receiving data from the other of said memory buses, whereby said memory provides data for a high resolution display and whereby some data stored in said memory is used for remapping locations in said memory.

Claim 16

The memory defined by claim 12 wherein said circuit means comprises a multiplexer, said multiplexer selecting between said data from said selected one of said buses and bank switching signals coupled to said multiplexer.

Claim 17

The memory defined by claim 13 wherein said multiplexer is controlled by a logic circuit which is coupled to said address bus and said selected one of said buses.

Claim 18

The memory defined by claim 14 wherein said logic circuit causes said multiplexer to select said bank switching signals each time said processor switches an OP code.

Claim 19

In a digital computer with a memory, which is used in conjunction with a raster scanned display, said display including a digital counter which provides a vertical count representative of the horizontal line scanned by the beam for said display, said memory providing data for displaying rows of characters, an addressing means coupled to said memory for scrolling displayed characters, comprising: an adder having a first and a second input terminal, the output of said adder providing a portion of an address signal for said memory, said first terminal of said adder being coupled to receive the lesser significant bits of said vertical count; said computer providing a periodically repeated sequence of digital numbers coupled to said second terminal of said adder, said sequence of digital numbers provided by said computer having a maximum value equal to the number of scanned lines in each of said rows, whereby the characters on said display are scrolled with a minimum of movement of data within said memory.

Claim 20

In a digital computer with a memory, which is used in conjunction with a raster scanned display, said display including a digital counter which provides a vertical count representative of the horizontal line scanned by the beam for said display, said memory providing data for displaying rows of characters, an addressing means coupled to said memory for scrolling displayed characters, comprising: an adder having a first and a second input terminal, the output of said adder providing a portion of an address signal for said memory, said first terminal of said adder being coupled to receive the lesser significant bits of said vertical count; said computer providing a periodically repeated sequence of digital numbers coupled to said second terminal of said adder, said sequence of digital numbers provided by said computer having a maximum value equal to the number of scanned lines in each of said rows, whereby the characters on said display are scrolled with a minimum of movement of data within said memory.

Claim 21

The addressing means defined by claim 16 wherein said sequence of digital numbers is incremented for each displayed frame.

Claim 22

In a ditital computer which includes a single chip central processing unit (CPU), a random-access memory (RAM), an address bus interconnecting said CPU and RAM such that said CPU addresses locations in said RAM, and a data bus coupled to said CPU and RAM, said CPU for certain functions addressing the zero page in said RAM by providing binary zeroes on certain lines of said address bus; an improvement comprising: a detection circuit for detecting said binary zeroes on said certain lines of said address bus; a register for storing digital signals, said register coupled to said data bus for receiving digital signals from said data bus; and, a multiplexer for selecting between said digital signals stored in said register and said certain lines of said address bus, said multiplexer being controlled by said detection circuit so as to select said register when said binary zeroes are detected on said certain lines of said address bus; whereby data for said certain functions normally stored on page one of said RAM, may be stored elsewhere in said RAM, and still easily addressed by said CPU.

Claim 23

In a ditital computer which includes a single chip central processing unit (CPU), a random-access memory (RAM), an address bus interconnecting said CPU and RAM such that said CPU addresses locations in said RAM, and a data bus coupled to said CPU and RAM, said CPU for certain functions addressing the zero page in said RAM by providing binary zeroes on certain lines of said address bus; an improvement comprising: a detection circuit for detecting said binary zeroes on said certain lines of said address bus; a register for storing digital signals, said register coupled to said data bus for receiving digital signals from said data bus; and, a multiplexer for selecting between said digital signals stored in said register and said certain lines of said address bus, said multiplexer being controlled by said detection circuit so as to select said register when said binary zeroes are detected on said certain lines of said address bus; whereby data for said certain functions normally stored on page one of said RAM, may be stored elsewhere in said RAM, and still easily addressed by said CPU.

Claim 24

The improvement defined by claim 18 wherein one of said stored signals from said register is coupled to said multiplexer through an exclusive OR gate, said gate being coupled to one of said certain lines of said address bus.

Claim 25

The improvement defined by claim 18 or 19 wherein said computer provides an alternate stack signal and wherein said detection circuit also detects addresses for page one on said address bus, and said multiplexer selects said register if said page one addresses are detected and said alternate stack signal is in a predetermined state.

Claim 26

In a digital computer which includes a central processing unit (CPU), a random-access memory (RAM), an address bus interconnecting said CPU and RAM such that said CPU addresses locations in said RAM and a data bus interconnecting said CPU and RAM, said CPU for certain functions addressing predetermined locations in said RAM with a predetermined range of address signals, an improvement comprising: detection means for detecting said predetermined range of address signals, coupled to said address bus; register means for storing digital signals, coupled to said data bus, and; switching means for coupling said digital signals stored in said register means to said address bus when said detection means detects said predetermined range of said address signals, said switching means also for coupling said digital signals stored in said register means to said address bus when a certain direct memory access (DMA) signal is in a predetermined state; a read-only memory (ROM) coupled between said address bus and said data bus, said ROM in response to signals on said address bus providing instructions to said CPU on said data bus to cause said CPU to increment address signals when said DMA signal is in said predetermined state; said register providing a pointer for locations in said RAM when said DMA signal is in said predetermined state, and said register providing RAM address signals when said certain functions are selected by said CPU, whereby data for said certain functions normally stored by said CPU in said predetermined locations may be stored elsewhere in said RAM, thereby enhancing the performance of said computer.

Claim 27

In a digital computer which includes a central processing unit (CPU), a random-access memory (RAM), an address bus interconnecting said CPU and RAM such that said CPU addresses locations in said RAM and a data bus interconnecting said CPU and RAM, said CPU for certain functions addressing predetermined locations in said RAM with a predetermined range of address signals, an improvement comprising: detection means for detecting said predetermined range of address signals, coupled to said address bus; register means for storing digital signals, coupled to said data bus, and; switching means for coupling said digital signals stored in said register means to said address bus when said detection means detects said predetermined range of said address signals, said switching means also for coupling said digital signals stored in said register means to said address bus when a certain direct memory access (DMA) signal is in a predetermined state; a read-only memory (ROM) coupled between said address bus and said data bus, said ROM in response to signals on said address bus providing instructions to said CPU on said data bus to cause said CPU to increment address signals when said DMA signal is in said predetermined state; said register providing a pointer for locations in said RAM when said DMA signal is in said predetermined state, and said register providing RAM address signals when said certain functions are selected by said CPU, whereby data for said certain functions normally stored by said CPU in said predetermined locations may be stored elsewhere in said RAM, thereby enhancing the performance of said computer.

Claim 28

The improvement defined by claim 21 wherein said switching means comprise a multiplexer which selects said register when said detection means detects all binary zeroes or when said DMA signal is in said predetermined state.