Patent US4383293A successfully refreshed from Google Patents.
US4383293A
Expired / Lapsed
US
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Isolated DC current sense circuit
Assignee: TRACEWELL ELECTRONICS Inc
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Filing: 1981-11-16
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Granted: 1983-05-10
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Expires: 2001-11-16
Abstract
Abstract An inverter circuit is disclosed in which the alternating current output is rectified to become a DC power supply with a regulated output voltage. The inverter is controlled to limit the peak current conducted by the power semiconductors and a current limit circuit is provided to limit the DC output current. The invention provides an output current sensing circuit utilizing a current transformer, with the primary winding thereof connected in the alternating current portion of the inverter circuit and with current flow in the primary winding proportional to the DC output. Rectifier means is provided to rectify the output of the secondary winding of the current transformer, and this is supplied across a first resistor. There is means to sample the voltage across this first resistor only during the conduction period of the power semiconductors. An integrating means is provided to integrate the sampled voltage and develop an output current signal for control of the output current from the inverter circuit. The foregoing abstract is merely a resume of one general application, is not a complete discussion of all principles of operation or applications, and is not to be construed as a limitation on the scope of the claimed subject matter.
Inventors
- 👤 Ronald H. Randall
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 20:21
CPC Classifications
H; H02; H02M; H02M3/00; H02M3/22; H02M3/24; H02M3/28; H02M3/325; H02M3/335; H02M3/337; H02M3/3376; H02M1/00; H02M1/0003; H02M1/0009
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
144 words
An output current sensing circuit for a converter circuit converting between AC and DC and having at least one controllable power semiconductor with a converter control circuit connected to control the conduction time of the semiconductor, said output current sensing circuit comprising, in combination: a current transformer having primary and secondary windings; means connecting said primary winding in an alternating current portion of the converter circuit for current flow therethrough proportional to an output of the converter circuit; rectifier means connected to rectify the output of the secondary winding of said current transformer; a first resistor connected to the output of said rectifier means; means to sample the voltage across said first resistor only during the conduction periods of the power semiconductor; and means to integrate said sampled voltage to develop an output current signal proportional to the output current from the converter circuit.
Claim 2
Dependent Claim
144 words
An output current sensing circuit for a converter circuit converting between AC and DC and having at least one controllable power semiconductor with a converter control circuit connected to control the conduction time of the semiconductor, said output current sensing circuit comprising, in combination: a current transformer having primary and secondary windings; means connecting said primary winding in an alternating current portion of the converter circuit for current flow therethrough proportional to an output of the converter circuit; rectifier means connected to rectify the output of the secondary winding of said current transformer; a first resistor connected to the output of said rectifier means; means to sample the voltage across said first resistor only during the conduction periods of the power semiconductor; and means to integrate said sampled voltage to develop an output current signal proportional to the output current from the converter circuit.
Claim 3
Dependent Claim
21 words
An output current sensing circuit as set forth in claim 1, wherein said sampling means includes a bidirectionally conducting control semiconductor.
Claim 4
Dependent Claim
36 words
An output current sensing circuit as set forth in claim 1, wherein said sampling means includes bias means biasing said control semiconductor into conduction substantially simultaneously with conduction of the power semiconductor of the converter circuit.
Claim 5
Dependent Claim
18 words
An output current sensing circuit as set forth in claim 1, wherein said integrating means includes capacitive means.
Claim 6
Dependent Claim
43 words
An output current sensing circuit as set forth in claim 1, wherein said sampling means includes an FET transistor connected to said first resistor, and biasing means connected to cause conduction of said transistor substantially simultaneously with the at least one power semiconductor.
Claim 7
Dependent Claim
33 words
An output current sensing circuit as set forth in claim 5, wherein said integrating means includes a second resistor and a capacitor connected for current flow therethrough concurrently with conduction of said transistor.
Claim 8
Dependent Claim
195 words
An output current sensing circuit for a converter circuit converting between AC and DC and having at least one controllable power semiconductor with a converter control circuit connected to control the conduction time of the semiconductor, said output current sensing circuit comprising, in combination: a current transformer having primary and secondary windings; means connecting said primary winding in an alternating current portion of the converter circuit for current flow therethrough proportional to an output of the converter circuit; rectifier means connected to rectify the output of the secondary winding of said current transformer; a first resistor connected to the output of said rectifier means to develop thereacross a DC signal; a bidirectionally conductive control semiconductor having first and second main electrodes and a control electrode and connected to said first resistor; means connecting the output of said control semiconductor main electrodes through a load; a bias resistor connected to said control electrode; and means connecting said bias resistor to the converter circuit at a point responsive to the conduction of the at least one converter power semiconductor to develop a control bias for said control semiconductor to develop an output current signal across said load.
Claim 9
Dependent Claim
195 words
An output current sensing circuit for a converter circuit converting between AC and DC and having at least one controllable power semiconductor with a converter control circuit connected to control the conduction time of the semiconductor, said output current sensing circuit comprising, in combination: a current transformer having primary and secondary windings; means connecting said primary winding in an alternating current portion of the converter circuit for current flow therethrough proportional to an output of the converter circuit; rectifier means connected to rectify the output of the secondary winding of said current transformer; a first resistor connected to the output of said rectifier means to develop thereacross a DC signal; a bidirectionally conductive control semiconductor having first and second main electrodes and a control electrode and connected to said first resistor; means connecting the output of said control semiconductor main electrodes through a load; a bias resistor connected to said control electrode; and means connecting said bias resistor to the converter circuit at a point responsive to the conduction of the at least one converter power semiconductor to develop a control bias for said control semiconductor to develop an output current signal across said load.
Claim 10
Dependent Claim
20 words
An output current sensing circuit as set forth in claim 1, wherein said control semiconductor is a field effect transistor.
Claim 11
Dependent Claim
30 words
An output current sensing circuit as set forth in claim 7, including a Zener diode connected to said bias resistor to limit the bias voltage applied to said control semiconductor.
Claim 12
Dependent Claim
21 words
An output current sensing circuit as set forth in claim 7, wherein said bias resistor is connected to said first resistor.
Claim 13
Dependent Claim
26 words
An output current sensing circuit as set forth in claim 7, wherein said bias resistor is connected to the secondary winding side of the power transformer.
Claim 14
Dependent Claim
34 words
An output current sensing circuit as set forth in claim 7, wherein said power transformer has a secondary winding and said current transformer winding is connected in series with said power transformer secondary winding.
Claim 15
Dependent Claim
21 words
An output current sensing circuit as set forth in claim 7, wherein said load includes a second resistor and a capacitor.
Claim 16
Dependent Claim
24 words
An output current sensing circuit as set forth in claim 13, wherein said first resistor and said capacitor are connected to a common conductor.
Claim 17
Dependent Claim
155 words
A combined peak current detection and output current sensing circuit for a converter circuit having at least one controllable power semiconductor connected to conduct through the primary winding of a power transformer with a converter control circuit connected to control the conduction time of the power semiconductor, said detection and sensing circuit comprising, in combination: a current transformer having primary and secondary windings; means connecting said current transformer primary winding for current flow therethrough proportional to an output of said converter; rectifier means to rectify the output of the secondary winding of said current transformer; a first resistor connected to the output of said rectifier means to develop thereacross a peak current detection signal; means to sample the voltage across said first resistor only during the conduction periods of the at least one semiconductor; and means to integrate said sampled voltage to develop a sensing signal proportional to an output current of the converter circuit.
Claim 18
Dependent Claim
155 words
A combined peak current detection and output current sensing circuit for a converter circuit having at least one controllable power semiconductor connected to conduct through the primary winding of a power transformer with a converter control circuit connected to control the conduction time of the power semiconductor, said detection and sensing circuit comprising, in combination: a current transformer having primary and secondary windings; means connecting said current transformer primary winding for current flow therethrough proportional to an output of said converter; rectifier means to rectify the output of the secondary winding of said current transformer; a first resistor connected to the output of said rectifier means to develop thereacross a peak current detection signal; means to sample the voltage across said first resistor only during the conduction periods of the at least one semiconductor; and means to integrate said sampled voltage to develop a sensing signal proportional to an output current of the converter circuit.
Claim 19
Dependent Claim
20 words
A combined detection and sensing circuit as set forth in claim 15, wherein said primary windings are connected in series.
Claim 20
Dependent Claim
36 words
A combined detection and sensing circuit as set forth in claim 15, including means connecting said peak current detection signal to the converter control circuit to control the peak current of the at least one semiconductor.
Claim 21
Dependent Claim
33 words
A combined detection and sensing circuit as set forth in claim 15, including means connecting said output current sensing signal to the converter control circuit to control the output of the converter circuit.
Claim 22
Dependent Claim
21 words
A combined detection and sensing circuit as set forth in claim 15, wherein said integrating means includes resistive and capacitive means.
Claim 23
Dependent Claim
37 words
A combined detection and sensing circuit as set forth in claim 15, wherein said integrating means includes a capacitor charged by said sampling means through a resistance, and the voltage across said capacitor being said sensing signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-05-09 | 1986-11-08 | 1987-05-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-05-09 | 1990-11-08 | 1991-05-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-05-09 | 1994-11-08 | 1995-05-10 | $7700.00 | Window Closed / Lapsed |