US4382297A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Demultiplex receiver apparatus
Assignee: AT&T Inc
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Filing: 1980-10-24
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Granted: 1983-05-03
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Expires: 2000-10-24
Abstract
Abstract Accurate recovery of constituent data streams from a multiplexed serial data stream in which each symbol includes a nonintegral number of frames is accomplished by combining a coherently detected timing signal, which is a component of the received serial data stream, together with a bit clock signal and a symbol clock signal to locate a predetermined bit position within each frame. When the location of the predetermined bit position is determined, frame synchronization is complete and the constituent data streams are correctly demultiplexed from the multiplexed serial data stream. The timing signal has a pulse rate equal to the greatest common divisor of the frame and symbol rates.
Inventors
- 👤 Cecil W. Farrow
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:04
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0602; H04J3/0605; H04J3/0608; H04J3/16; H04J3/1605; H04J3/1623; H04J3/1629; H04J3/1647
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
250 words
Receiver apparatus of the type including means (102) responsive to an input signal (RS) for generating a corresponding serial bit stream (SDS) having a plurality of bits arranged in consecutive symbols and also for generating a symbol clock signal (SC) having a first pulse rate related to a rate of occurrence for each symbol and a bit clock signal (BC) having a second pulse rate related to a rate of occurrence for each bit in the corresponding serial bit stream, the serial bit stream also capable of being partitioned into consecutive frames, the receiver apparatus characterized by, means (120) responsive to the bit clock signal for generating at least one frame clock signal (e.g., FC1, FC2, FC3, FC4) having a third pulse rate related to a rate of occurrence of consecutive frame, in the corresponding serial bit stream, wherein M/N is a nonintegral rational number, means (104, 105) responsive to the input signal for generating a timing signal (TS) having a pulse rate related in a prescribed manner to the first and third pulse rates, and means (103, 110, 121) jointly responsive to the symbol clock signal and the timing signal for controlling the at least one frame clock signal to have a phase synchronized with a predetermined bit position (A 0 , A 1 , A 2 , A 3 ) of each frame, so that a predetermined transition of the frame clock signal occurs at the predetermined bit position of each frame in the corresponding serial bit stream.
Claim 2
Dependent Claim
250 words
Receiver apparatus of the type including means (102) responsive to an input signal (RS) for generating a corresponding serial bit stream (SDS) having a plurality of bits arranged in consecutive symbols and also for generating a symbol clock signal (SC) having a first pulse rate related to a rate of occurrence for each symbol and a bit clock signal (BC) having a second pulse rate related to a rate of occurrence for each bit in the corresponding serial bit stream, the serial bit stream also capable of being partitioned into consecutive frames, the receiver apparatus characterized by, means (120) responsive to the bit clock signal for generating at least one frame clock signal (e.g., FC1, FC2, FC3, FC4) having a third pulse rate related to a rate of occurrence of consecutive frame, in the corresponding serial bit stream, wherein M/N is a nonintegral rational number, means (104, 105) responsive to the input signal for generating a timing signal (TS) having a pulse rate related in a prescribed manner to the first and third pulse rates, and means (103, 110, 121) jointly responsive to the symbol clock signal and the timing signal for controlling the at least one frame clock signal to have a phase synchronized with a predetermined bit position (A 0 , A 1 , A 2 , A 3 ) of each frame, so that a predetermined transition of the frame clock signal occurs at the predetermined bit position of each frame in the corresponding serial bit stream.
Claim 3
Dependent Claim
56 words
The apparatus as defined in claim 1 further characterized by, means (122, 123) jointly responsive to the bit clock signal and the frame clock signal synchronized in phase with the predetermined bit position of each frame for converting the corresponding serial bit stream into not more than N constituent serial bit streams (CDSA, CDSB, CDSC, CDSD).
Claim 4
Dependent Claim
26 words
The apparatus as defined in claim 2 wherein the pulse rate of the timing signal is a common divisor of the first and third pulse rates.
Claim 5
Dependent Claim
29 words
The apparatus as defined in claim 3 wherein the timing signal generating means includes an envelope detector for amplitude demodulating the input signal to recover the timing signal therefrom.
Claim 6
Dependent Claim
23 words
The apparatus as defined in claim 3 wherein the common divisor is the greatest common divisor of the first and third pulse rates.
Claim 7
Dependent Claim
80 words
The apparatus as defined in claim 5 wherein the at least one frame clock signal generating means generates a plurality of frame clock signals, each frame clock signal having a predetermined phase and the third pulse rate, and the means for controlling includes, means responsive to the symbol clock signal and the timing signal for selecting one frame clock signal of the plurality of frame clock signals having a predetermined transition occurring at the predetermined bit position of each frame.
Claim 8
Dependent Claim
91 words
The apparatus as defined in claim 6 wherein the means for selecting includes, means (103, 110) responsive to the symbol clock signal and the timing signal for generating at least one control signal (X, Y) employed to select the one frame clock signal from the plurality of frame clock signals which identifies the predetermined bit position of each frame in the corresponding serial bit stream, and means (121) jointly responsive to the at least one control signal for selecting the one frame clock signal from the plurality of frame clock signals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-05-02 | 1986-11-01 | 1987-05-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-05-02 | 1990-11-01 | 1991-05-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-05-02 | 1994-11-01 | 1995-05-03 | $7700.00 | Window Closed / Lapsed |