Data communication system

Claim 1

A DATA TRANSMITTER COMPRISING A SOURCE OF BINARY "1" AND "0" SIGNALS IN A SEQUENCE OF DIBIT PAIRS CHOSEN FROM THE COMBINATIONS 10, 00, 01 AND 11; A TIMING CIRCUIT PRODUCING A DIBIT SYNCHRONIZING SIGNAL; DIGITAL LOGIC MEANS CONTROLLED BY SAID TIMING CIRCUIT FOR SYNCHRONOUSLY GENERATING A FEW CYCLES OF A CARRIER WAVE EVERY DIBIT PERIOD, EACH SUCCESSIVE FEW CYCLES BEING SHIFTED IN RELATIVE PHASE AT LEAST 45 DEGREES EVEN IN THE ABSENCE OF AN INPUT SIGNAL; MEANS FOR APPLYING SAID DIBIT SIGNALS TO SAID LOGIC MEANS AS AN INPUT SIGNAL TO CAUSE SAID LATTER MEANS TO IMPART ADDITIONAL RELATIVE PHASE SHIFTS TO SAID SUCCESSIVE FEW CYCLES OF CARRIER WAVE OF 0, 90, 180 OR 270 DEGREES ACCORDING TO A FIXED RELATIONSHIP BETWEEN SAID DIBIT COMBINATIONS AND SAID ADDITIONAL PHASE SHIFTS; AND MEANS FOR AMPLITUDE MODULATING THE OUTPUT OF SAID LOGIC MEANS BY A COSINE WAVE OCCURRING AT HALF SAID DIBIT RATE.