US4382289A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Toshiba Corp
•
Filing: 1981-09-02
•
Granted: 1983-05-03
•
Expires: 2001-09-02
Abstract
Abstract A semiconductor memory device comprises an insulation layer and a plurality of polycrystalline silicon layer regions formed on the insulation layer. The polycrystalline silicon layer region includes a semiconductor element region and a meltable semiconductor fuse link region. The two regions are integrated with each other to constitute a unit memory cell. A plurality of unit memory cells connected between bit lines and word lines jointly constitute a memory device. Where required data is written in the memory device, then the semiconductor fuse region of a specified unit memory cell is melted away.
Inventors
- 👤 Shinji Saitoh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:58
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/14; H; H10; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/493; H10B; H10B20/00; H10B20/20; H10B20/25; Y; Y10; Y10S; Y10S257/00; Y10S257/926
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
69 words
A semiconductor memory device which comprises: an insulation layer; and a plurality of polycrystalline silicon layer regions formed on said insulation layer, and wherein each polycrystalline silicon layer region includes a semiconductor element region and a semiconductor fuse region containing a meltable fuse link; and said semiconductor element region and said semiconductor fuse region are integrated with each other to constitute a memory cell of said semiconductor memory device.
Claim 2
Dependent Claim
69 words
A semiconductor memory device which comprises: an insulation layer; and a plurality of polycrystalline silicon layer regions formed on said insulation layer, and wherein each polycrystalline silicon layer region includes a semiconductor element region and a semiconductor fuse region containing a meltable fuse link; and said semiconductor element region and said semiconductor fuse region are integrated with each other to constitute a memory cell of said semiconductor memory device.
Claim 3
Dependent Claim
18 words
The semiconductor memory device according to claim 1, wherein said insulation layer is formed on a semiconductor substrate.
Claim 4
Dependent Claim
16 words
The semiconductor memory device according to claim 1, wherein said semiconductor element region includes a diode.
Claim 5
Dependent Claim
17 words
The semiconductor memory device according to claim 1, wherein said semiconductor element region includes a bipolar transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-05-02 | 1986-11-01 | 1987-05-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-05-02 | 1990-11-01 | 1991-05-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-05-02 | 1994-11-01 | 1995-05-03 | $7700.00 | Window Closed / Lapsed |