US4382197A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Logic having inhibit mean preventing erroneous operation circuit
Assignee: NEC Corp
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Filing: 1980-07-30
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Granted: 1983-05-03
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Expires: 2000-07-30
Abstract
Abstract A logic circuit operable without erroneous operation is disclosed. The logic circuit comprises a first and a second switching transistor operating in response to the same signal, a first logic gate including an input transistor receiving a signal derived from the first switching transistor and a second logic gate receiving a signal derived from the second switching signal, in which the signal derived from the first switching transistor is independently fed to the first logic gate.
Inventors
- 👤 Noboru Kiyozuka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 10:21
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00307
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
177 words
A logic circuit comprising a current source, first and second transistors, emitters of said first and second transistors being coupled to said current source in common, first means for operatively supplying a base of said first transistor with a reference voltage, a value of said reference voltage making said first transistor conductive, second means coupled to a collector of said second transistor and responsive to a conducting state of said second transistor for inhibiting said first means from supplying said reference voltage thereby to make said first transistor non-conducting, a third transistor having an emitter coupled to the emitter of said second transistor and a base coupled to the base of said second transistor, third means for applying an input signal to the bases of said second and third transistors in common, a first logic circuit coupled to a collector of said third transistor and controlled by the conducting state of said third transistor, and a second logic circuit coupled to a collector of said first transistor and controlled by the conducting state of said first transistor.
Claim 2
Dependent Claim
177 words
A logic circuit comprising a current source, first and second transistors, emitters of said first and second transistors being coupled to said current source in common, first means for operatively supplying a base of said first transistor with a reference voltage, a value of said reference voltage making said first transistor conductive, second means coupled to a collector of said second transistor and responsive to a conducting state of said second transistor for inhibiting said first means from supplying said reference voltage thereby to make said first transistor non-conducting, a third transistor having an emitter coupled to the emitter of said second transistor and a base coupled to the base of said second transistor, third means for applying an input signal to the bases of said second and third transistors in common, a first logic circuit coupled to a collector of said third transistor and controlled by the conducting state of said third transistor, and a second logic circuit coupled to a collector of said first transistor and controlled by the conducting state of said first transistor.
Claim 3
Dependent Claim
28 words
The circuit according to claim 1, in which said first logic circuit includes a first input transistor receiving at its base a signal derived from said third transistor.
Claim 4
Dependent Claim
22 words
The circuit according to claim 2, further comprising first and second output terminals respectively coupled to said first and second logic circuits.
Claim 5
Dependent Claim
73 words
The circuit according to claim 3, said circuit further comprising a first power supply terminal comprising said operating voltage source and a second power supply terminal, in which said first means includes a series circuit having an impedance element and a current source transistor coupled between said first and second power supply terminals and a circuit connection for coupling an intermediary point of said series circuit and the base of said first transistor.
Claim 6
Dependent Claim
30 words
The circuit according to claim 4, in which said second means includes a diode coupled between an intermediary point of said series circuit and the collector of said second transistor.
Claim 7
Dependent Claim
173 words
A logic circuit further comprising an input terminal, a first output terminal, a second output terminal, a first switching transistor, a second switching transistor, means coupled to said input terminal for applying an input logic signal to bases of said first and second switching transistors in common, an emitter of said first switching transistor being coupled to an emitter of said second switching transistor, a first logic gate having a first input and coupled to a collector of said first switching transistor and a first output end connected to said first output terminal, said first logic gate including an input transistor having a base connected to said first input end and controlled by said first switching transistor, and a second logic gate having a second input end coupled to a collector of said second switching transistor and a second output end connected to said second output terminal, said second logic gate being independent from the output of said first logic gate at said first output end and controlled by said second switching transistor.
Claim 8
Dependent Claim
173 words
A logic circuit further comprising an input terminal, a first output terminal, a second output terminal, a first switching transistor, a second switching transistor, means coupled to said input terminal for applying an input logic signal to bases of said first and second switching transistors in common, an emitter of said first switching transistor being coupled to an emitter of said second switching transistor, a first logic gate having a first input and coupled to a collector of said first switching transistor and a first output end connected to said first output terminal, said first logic gate including an input transistor having a base connected to said first input end and controlled by said first switching transistor, and a second logic gate having a second input end coupled to a collector of said second switching transistor and a second output end connected to said second output terminal, said second logic gate being independent from the output of said first logic gate at said first output end and controlled by said second switching transistor.
Claim 9
Dependent Claim
21 words
The circuit according to claim 6, further comprising a third logic gate receiving the signal derived from said second switching transistor.
Claim 10
Dependent Claim
39 words
The circuit according to claim 7, further comprising a first output terminal coupled to said first logic gate, a second output terminal coupled to said second logic gate and a third output terminal coupled to said third logic gate.
Claim 11
Dependent Claim
28 words
The circuit according to claim 6, in which said second logic gate includes an input transistor receiving at its emitter a signal derived from said second switching transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-05-02 | 1986-11-01 | 1987-05-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-05-02 | 1990-11-01 | 1991-05-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-05-02 | 1994-11-01 | 1995-05-03 | $7700.00 | Window Closed / Lapsed |