Patent US4579858A successfully refreshed from Google Patents.
Patent US4380756A successfully refreshed from Google Patents.
US4380756A
Expired / Lapsed
US
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Charge redistribution circuit having reduced area
Assignee: Microsemi Semiconductor ULC
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Filing: 1980-12-22
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Granted: 1983-04-19
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Expires: 2000-12-22
Abstract
Abstract A codec using charge redistribution techniques between two groups of banks of weighted capacitors, which requires substantially reduced chip area as compared to previous codecs of this type. A switching scheme by which the capacitors are switched between themselves to various leads allows the elimination of the previously required largest capacitor of one bank and its replacement by a capacitor of one eighth its value and size (as well as several very small capacitors) in the other bank. The switching scheme also allows the use of only one reference voltage level, whereas in the past two were required.
Inventors
- 👤 Adrian D. Worsman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:25
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/02
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
285 words
A charge redistribution circuit for translation of an input signal comprising: (a) a first plurality of capacitors, one terminal of each capacitor being connected together, (b) means for switching said one terminal to a first reference voltage, (c) means for selectively switching the other terminal of each capacitor between a first lead and a second lead, (d) means for selectively switching the first lead between a source of said input signal, said first reference voltage, and a high impedance, (e) a second plurality of capacitors, one terminal of each capacitor being connected together, (f) a buffer having its input connected to said one terminal of the second plurality of capacitors, and its output connected to said second lead, (g) means for switching the input of the buffer to said first reference voltage, (h) means for selectively switching the other terminal of each of the second plurality of capacitors to a third or a fourth lead, (i) means for switching the third and fourth leads interchangeably to the first reference voltage and to a second reference voltage having a single polarity with respect to said first reference voltage, whereby upon switching of sequences of said other terminal of capacitors of the first plurality of capacitors between the first and second leads, a distribution of charge is effected therebetween, and upon switching of sequences of said other terminal of capacitors of the second plurality of capacitors between the third and fourth leads a distribution of charge is effected therebetween, and (j) output means for carrying an output signal from said one terminal of the first plurality of capacitors, resulting from the distribution of charge between the first capacitors and the distribution of charge between the second capacitors.
Claim 2
Dependent Claim
285 words
A charge redistribution circuit for translation of an input signal comprising: (a) a first plurality of capacitors, one terminal of each capacitor being connected together, (b) means for switching said one terminal to a first reference voltage, (c) means for selectively switching the other terminal of each capacitor between a first lead and a second lead, (d) means for selectively switching the first lead between a source of said input signal, said first reference voltage, and a high impedance, (e) a second plurality of capacitors, one terminal of each capacitor being connected together, (f) a buffer having its input connected to said one terminal of the second plurality of capacitors, and its output connected to said second lead, (g) means for switching the input of the buffer to said first reference voltage, (h) means for selectively switching the other terminal of each of the second plurality of capacitors to a third or a fourth lead, (i) means for switching the third and fourth leads interchangeably to the first reference voltage and to a second reference voltage having a single polarity with respect to said first reference voltage, whereby upon switching of sequences of said other terminal of capacitors of the first plurality of capacitors between the first and second leads, a distribution of charge is effected therebetween, and upon switching of sequences of said other terminal of capacitors of the second plurality of capacitors between the third and fourth leads a distribution of charge is effected therebetween, and (j) output means for carrying an output signal from said one terminal of the first plurality of capacitors, resulting from the distribution of charge between the first capacitors and the distribution of charge between the second capacitors.
Claim 3
Dependent Claim
72 words
A circuit as defined in claim 1, in which the output means is comprised of a comparator, having a first input connected to said one terminal of the first plurality of capacitors, and a second input connected to the first reference voltage, and means for providing an output signal having a level below or above predetermined levels at the output of the comparator for designating the sign of an encoded output signal.
Claim 4
Dependent Claim
50 words
A circuit as defined in claim 1, in which the output means is comprised of a sample and hold circuit having its input connected to said one terminal of the first plurality of capacitors for providing elements of an output signal at its output for conversion to an analog signal.
Claim 5
Dependent Claim
101 words
A circuit as defined in claim 1, in which the output means is comprised of a comparator, having a first input connected to said one terminal of the first plurality of capacitors, and a second input connected to the first reference voltage, means for providing an output signal having a level above or below predetermined levels at the output of the comparator, and a sample and hold circuit having its input connected in a circuit to said one terminal of the first plurality of capacitors for providing elements of an output signal at its output for conversion to an analog signal.
Claim 6
Dependent Claim
59 words
A circuit as defined in claim 2 or 4, in which said first and second inputs of the comparator are its inverting and noninverting inputs respectively, said first reference voltage is ground, and said second reference voltage is a positive voltage relative to ground having amplitude at least as high as the maximum amplitude of the input signal voltage.
Claim 7
Dependent Claim
87 words
A circuit as defined in claim 1, in which the capacitance of each capacitor of the first plurality of capacitors is respectively C, C, 2C, 4C, 8C, 16C, 32C and 64C, said one terminal of the first capacitor having capacitance C being switchable to said first terminal of the remaining ones of the first plurality of capacitors, and in which the capacitance of each capacitor of the second plurality of capacitors is respectively 1/2C, 1/2C, C, C, 2C, 4C, 8C, and 16C, where C is a constant.
Claim 8
Dependent Claim
275 words
A circuit as defined in claim 1, 2 or 4, in which the input signal is a segment of an analog signal the capacitance of each capacitor of the first plurality of capacitors is respectively C, C, 2C, 4C, 8C, 16C, 32C and 64C, said one terminal of the first capacitor having capacitance C being switchable to said first terminal of the remaining ones of the first plurality of capacitors, and in which the capacitance of each capacitor of the second plurality of capacitors is respectively 1/2C, 1/2C, C, C, 2C, 4C, 8C and 16C, where C is a constant and further including means for switching capacitors of the first plurality of capacitors from the first lead to the second lead after application of an analog sample of the input signal until the comparator switches its state, and of the second plurality of capacitors from the fourth lead to the third lead, after switching the first plurality of capacitors except said first capacitor C from the second lead to the high impedance, until the comparator again switches its state, the voltage level at which the comparator last switches state, being a larger amplitude decision level value, is equal to V.sub.r [-0.5/128+(2(.sup.s-1)/128×(17+n)/33)] where V r is the second reference voltage s varies from 1 to 8 as the first plurality of capacitors is switched from the first to the second lead and n varies from 0 to 15 as the second plurality of capacitors is switched from the fourth to the third lead whereby the designations of the switched capacitors when the comparator last switches state determines an output PCM word corresponding to said analog sample.
Claim 9
Dependent Claim
213 words
A circuit as defined in claim 1, 3 or 4, in which the input signal is a PCM word designative of particular capacitors to be switched, the capacitance of each capacitor of the first plurality of capacitors is respectively C, C, 2C, 4C, 8C, 16C, 32C and 64C, said one terminal of the first capacitor having capacitance C being switchable to said first terminal of the remaining ones of the first plurality of capacitors, and in which the capacitance of each capacitor of the second plurality of capacitors is respectively (1/2)C, (1/2)C, C, C, 2C, 4C, 8C and 16C, where C is a constant, and further including means for switching capacitors of the first and second plurality of capacitors from the first to the second lead and from the third to the fourth lead respectively as designated by the PCM word, the output voltage level being equal to V.sub.r [-0.5/128+(2(.sup.s-1)/128×(16.5+n)/33)] where V r is the second reference voltage s is a number between 1 to 8 designating the most significant capacitor of the first plurality of capacitors switched from the first to the second lead and n is a number between 0 to 15 designating the most significant capacitors of the second plurality of capacitors switched from the fourth to the third lead.
Claim 10
Independent Claim
476 words
A method of encoding a sample of an input signal having an unknown amplitude which is lower than a predetermined maximum comprising: (a) applying a sample of the input signal to one common terminal of a first plurality of capacitors connected in parallel and connecting the other common terminal to ground, whereby the capacitors are charged to the voltage of the sample of the input signal, the respective capacitance values of the first plurality of capacitors being C, C, 2C, 4C, 8C 16C, 32C and 64C, where C is a constant, (b) connecting said one common terminal to ground while switching said other common terminal from ground to the input of a comparator, the other input terminal of the comparator being connected to ground, (c) detecting the sign of the output signal of the comparator, (d) connecting one common terminal of a second plurality of capacitors to ground, (e) connecting the other common terminal of the second plurality of capacitors to one of ground in the event the sign of the output signal of the comparator is positive, or to a supply voltage at least as high as said predetermined maximum in the event the sign of the output signal of the comparator is negative, the respective capacitance values of the second plurality of capacitors being 1/2C, 1/2C, C, C, 2C, 4C, 8C and 16C, where C is said constant, (f) switching said other terminal of a 1/2C and a 16C capacitor to the other of the supply voltage or ground, (g) switching said one terminal of a C capacitor of the first plurality of capacitors to ground and its other terminal the first common terminal of the second plurality of capacitors via the output of a buffer, (h) switching said other terminals of the remaining ones of the first plurality of capacitors to a high impedance, and said one common terminal thereof to ground, (i) switching said one terminal of the latter C capacitor to said one common terminal of the first plurality of terminals, (j) reswitching said 1/2C capacitor to the first of ground or the voltage supply, (k) switching capacitors of the first plurality of capacitors in parallel with said latter C capacitor until the output signal of the comparator changes states, (l) switching capacitor having the most significant capacitance from a connection in parallel with said latter C capacitor to a connection in parallel with the remaining first plurality of capacitors, (m) switching capacitors of the second plurality of capacitors in parallel with said 16C capacitor of the second plurality of capacitors until the output signal of the comparator changes state, whereby the binary value identity of the switched capacitors at the last change of state of the output signal of the comparator designates the digital identification of a PCM word corresponding to the amplitude of the sample of the input signal.
Claim 11
Independent Claim
476 words
A method of encoding a sample of an input signal having an unknown amplitude which is lower than a predetermined maximum comprising: (a) applying a sample of the input signal to one common terminal of a first plurality of capacitors connected in parallel and connecting the other common terminal to ground, whereby the capacitors are charged to the voltage of the sample of the input signal, the respective capacitance values of the first plurality of capacitors being C, C, 2C, 4C, 8C 16C, 32C and 64C, where C is a constant, (b) connecting said one common terminal to ground while switching said other common terminal from ground to the input of a comparator, the other input terminal of the comparator being connected to ground, (c) detecting the sign of the output signal of the comparator, (d) connecting one common terminal of a second plurality of capacitors to ground, (e) connecting the other common terminal of the second plurality of capacitors to one of ground in the event the sign of the output signal of the comparator is positive, or to a supply voltage at least as high as said predetermined maximum in the event the sign of the output signal of the comparator is negative, the respective capacitance values of the second plurality of capacitors being 1/2C, 1/2C, C, C, 2C, 4C, 8C and 16C, where C is said constant, (f) switching said other terminal of a 1/2C and a 16C capacitor to the other of the supply voltage or ground, (g) switching said one terminal of a C capacitor of the first plurality of capacitors to ground and its other terminal the first common terminal of the second plurality of capacitors via the output of a buffer, (h) switching said other terminals of the remaining ones of the first plurality of capacitors to a high impedance, and said one common terminal thereof to ground, (i) switching said one terminal of the latter C capacitor to said one common terminal of the first plurality of terminals, (j) reswitching said 1/2C capacitor to the first of ground or the voltage supply, (k) switching capacitors of the first plurality of capacitors in parallel with said latter C capacitor until the output signal of the comparator changes states, (l) switching capacitor having the most significant capacitance from a connection in parallel with said latter C capacitor to a connection in parallel with the remaining first plurality of capacitors, (m) switching capacitors of the second plurality of capacitors in parallel with said 16C capacitor of the second plurality of capacitors until the output signal of the comparator changes state, whereby the binary value identity of the switched capacitors at the last change of state of the output signal of the comparator designates the digital identification of a PCM word corresponding to the amplitude of the sample of the input signal.
References Cited (Backward Citations)
US4195282A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-04-18 | 1986-10-18 | 1987-04-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-04-18 | 1990-10-18 | 1991-04-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-04-18 | 1994-10-18 | 1995-04-19 | $7700.00 | Window Closed / Lapsed |