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US4380745A
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Digitally controlled temperature compensated oscillator system
Assignee: United States Department of the Navy
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Filing: 1980-11-07
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Granted: 1983-04-19
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Expires: 2000-11-07
Abstract
Abstract A crystal oscillator that is temperature compensated by digitally substrang a correction frequency from the running frequency of the crystal oscillator to provide the required operating frequency. The correction frequency is generated by a digital frequency synthesizer circuit which is controlled by the output of a programmable read-only memory which has been programmed to generate the required correction frequency for each temperature code over the operating temperature range. The temperature code is generated by gating a digital counter with the output of a monostable multivibrator which utilizes a thermistor to make its gate interval proportional to temperature.
Inventors
- 👤 Michael L. Barlow
- 👤 Alan L. Lindstrum
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:40
CPC Classifications
H; H03; H03L; H03L1/00; H03L1/02; H03L1/022; H03L1/026; H03K; H03K3/00; H03K3/01; H03K3/011; H03L1/027
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
200 words
A temperature-compensated oscillator system for producing a system output signal of a constant frequency, which comprises: (a) an oscillator having a known output frequency versus temperature characteristic; (b) a temperature sensor for producing a first output signal proportional to the temperature at which the oscillator is operating; (c) a temperature-controlled timer coupled to receive the first output signal, said temperature controlled timer producing a second output signal having a duration which is related to the temperature sensed by said temperature sensor; (d) means for converting said second output signal to a first binary number representing the temperature sensed by said temperature sensor; (e) a programmable memory coupled to receive said first binary number on its address input, the memory address identified by said first binary number containing a second binary number representing an error frequency to adjust the frequency of the output signal from the oscillator; (f) means for generating a signal having said error frequency in response to said second binary number, said means for generating coupled to receive said addressed second binary number; and (g) means for combining said signal at said error frequency with the output signal from said oscillator to produce said temperature-compensated system output signal.
Claim 2
Dependent Claim
200 words
A temperature-compensated oscillator system for producing a system output signal of a constant frequency, which comprises: (a) an oscillator having a known output frequency versus temperature characteristic; (b) a temperature sensor for producing a first output signal proportional to the temperature at which the oscillator is operating; (c) a temperature-controlled timer coupled to receive the first output signal, said temperature controlled timer producing a second output signal having a duration which is related to the temperature sensed by said temperature sensor; (d) means for converting said second output signal to a first binary number representing the temperature sensed by said temperature sensor; (e) a programmable memory coupled to receive said first binary number on its address input, the memory address identified by said first binary number containing a second binary number representing an error frequency to adjust the frequency of the output signal from the oscillator; (f) means for generating a signal having said error frequency in response to said second binary number, said means for generating coupled to receive said addressed second binary number; and (g) means for combining said signal at said error frequency with the output signal from said oscillator to produce said temperature-compensated system output signal.
Claim 3
Dependent Claim
46 words
A system as recited in claim 1 wherein said means for converting said second output signal to a first binary number comprises: (a) a binary counter coupled to be enabled by said second output signal and having its clock input coupled to the system output signal.
Claim 4
Dependent Claim
47 words
A system recited in claim 2 wherein said means for generating a signal having said error frequency includes: (a) a programmable frequency divider coupled to be programmed by said second binary number from said programmable memory and having its clock input coupled to the system output signals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-04-18 | 1986-10-18 | 1987-04-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-04-18 | 1990-10-18 | 1991-04-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-04-18 | 1994-10-18 | 1995-04-19 | $7700.00 | Window Closed / Lapsed |