Patent US4379985A successfully refreshed from Google Patents.
US4379985A
Expired / Lapsed
US
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Bipolar driver with illegal code detector
Assignee: Pitney Bowes Inc
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Filing: 1982-05-14
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Granted: 1983-04-12
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Expires: 2002-05-14
Abstract
Abstract A bipolar driver controls the operation of a reversible polarity load such as a motor. The driver links one terminal of the motor with either a positive or a negative potential power supply in response to processor command signals comprising a combination of logic levels appearing at a pair of driver input lines. The input lines are monitored to detect the presence of an illegal code combination which would otherwise function to simultaneously interconnect the load terminal with both positive and negative power supplies. The load terminal is linked to the power supplies by a separate power transistor for each power supply. Each power transistor is biased into conduction through a drive transistor. Upon detection of an illegal code, monitoring logic generates a signal which interrupts the emitter circuit of each of the drive transistors to inhibit both power transistors.
Inventors
- 👤 Vincent G. Coppola
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 18:48
CPC Classifications
H; H02; H02H; H02H7/00; H02H7/08; H02H7/0833; H02H7/0844
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
303 words
An interface for a processor, a reversible polarity load having two terminals the first of which terminals being tied to a substantially fixed reference level, and a pair of opposite polarity power supplies, the processor selectively transmitting one of several possible command signal codes to the interface, the signal codes designating different modes of operation of the load, the interface comprising: a first power switch means, the first power switch means selectively interconnecting the second of said terminals of the load and the power supply of one polarity, a second power switch means, the second switch means selectively interconnecting the second of said terminals and the power supply of opposite polarity, means receiving each signal code and (a) in response to a first signal code, forward biasing the first power switch means to interconnect the second of said terminals and the power supply of one polarity and reverse biasing the second power switch means such that the second of said terminals is not interconnected with the power supply of the opposite polarity, (b) in response to a second signal code, reversing the first power switch means such that the second of said terminals is not interconnected to the power supply of one polarity and forward biasing the second power, switch means to interconnect the second of said terminals and the power supply of the opposite polarity, and (c) in response to a third signal code, reverse biasing both power switch means such that the second of said terminals is not connected with either power supply, the interface further comprising illegal signal code inhibit means, the inhibit means including monitoring means receiving the signal codes and in response to an invalid signal code which would otherwise function to forward bias both power switch means, inhibiting the operation of both of said power switch means.
Claim 2
Dependent Claim
303 words
An interface for a processor, a reversible polarity load having two terminals the first of which terminals being tied to a substantially fixed reference level, and a pair of opposite polarity power supplies, the processor selectively transmitting one of several possible command signal codes to the interface, the signal codes designating different modes of operation of the load, the interface comprising: a first power switch means, the first power switch means selectively interconnecting the second of said terminals of the load and the power supply of one polarity, a second power switch means, the second switch means selectively interconnecting the second of said terminals and the power supply of opposite polarity, means receiving each signal code and (a) in response to a first signal code, forward biasing the first power switch means to interconnect the second of said terminals and the power supply of one polarity and reverse biasing the second power switch means such that the second of said terminals is not interconnected with the power supply of the opposite polarity, (b) in response to a second signal code, reversing the first power switch means such that the second of said terminals is not interconnected to the power supply of one polarity and forward biasing the second power, switch means to interconnect the second of said terminals and the power supply of the opposite polarity, and (c) in response to a third signal code, reverse biasing both power switch means such that the second of said terminals is not connected with either power supply, the interface further comprising illegal signal code inhibit means, the inhibit means including monitoring means receiving the signal codes and in response to an invalid signal code which would otherwise function to forward bias both power switch means, inhibiting the operation of both of said power switch means.
Claim 3
Dependent Claim
27 words
An interface constructed in accordance with claim 1 wherein the inhibit means includes means for inhibiting both power switch means in response to an invalid signal code.
Claim 4
Dependent Claim
49 words
An interface constructed in accordance with claim 1 wherein each of the power switch means comprises a power transistor, the means receiving each signal code including a driver transistor and including means for interconnecting the emitter-collector circuit of each driver transistor with the base of a respective power transistor.
Claim 5
Dependent Claim
31 words
An interface constructed in accordance with claim 3 wherein the inhibit means includes means for interrupting the emitter collector circuit of each driver transistor in response to an invalid signal code.
Claim 6
Dependent Claim
77 words
An interface constructed in accordance with claim 3 wherein each signal code comprises a pair of parallel loaded signals, the interface including a pair of input lines, one of the input lines receiving one of the signals and another input line receiving the other signal, means operatively interconnecting the base of one of the driver transistors with the one input line and means operatively interconnecting the base of the other driver transistor with the other input line.
Claim 7
Dependent Claim
73 words
An interface constructed in accordance with claim 5 wherein the monitoring means includes gate means operatively interconnected between the input lines, the gate means receiving the signal code and in respone to the presence of an invalid signal code generating an alarm signal, the means for interrupting the emitter-collector circuit of each driver transistor receiving an alarm signal and interrupting the emitter-collector circuit of each driver transistor in response to such alarm signal.
Claim 8
Dependent Claim
34 words
An interface constructed in accordance with claim 6 wherein the interface includes switch means for completing the emitter-collector circuit of each driver transistor, the interrupting means including means for reverse biasing the switch means.
Claim 9
Dependent Claim
17 words
An interface constructed in accordance with claim 7 wherein said substantially fixed reference level is electrical ground.
Claim 10
Dependent Claim
225 words
An interface for a processor, a plurality of reversible polarity loads each of said loads having two terminals the first of which terminals being tied to a substantially fixed reference level, and a pair of opposite polarity power supplies wherein the processor simultaneously transmits a like plurality of command signal codes to the interface, each transmitted code being associated with one of the loads, the interface including a like plurality of first power switch means, each first power switch means selectively interconnecting the second of said terminals of a respective load and the power supply of one polarity, a plurality of second power switch means, each second power switch means selectively interconnecting the second of said terminals of a respective load and the power supply of opposite polarity, the interface further including a like plurality of means receiving each signal code and interconnecting the second of said terminals of the respective load with one of the power supplies in accordance with the signal code, and illegal signal code inhibit means including a like plurality of monitoring means receiving the respective signal codes and in response to an invalid signal code inhibiting the operation of one of the plurality of first power switch means and one of the plurality of second power switch means, both of which power switch means are associated with the respective load.
Claim 11
Dependent Claim
225 words
An interface for a processor, a plurality of reversible polarity loads each of said loads having two terminals the first of which terminals being tied to a substantially fixed reference level, and a pair of opposite polarity power supplies wherein the processor simultaneously transmits a like plurality of command signal codes to the interface, each transmitted code being associated with one of the loads, the interface including a like plurality of first power switch means, each first power switch means selectively interconnecting the second of said terminals of a respective load and the power supply of one polarity, a plurality of second power switch means, each second power switch means selectively interconnecting the second of said terminals of a respective load and the power supply of opposite polarity, the interface further including a like plurality of means receiving each signal code and interconnecting the second of said terminals of the respective load with one of the power supplies in accordance with the signal code, and illegal signal code inhibit means including a like plurality of monitoring means receiving the respective signal codes and in response to an invalid signal code inhibiting the operation of one of the plurality of first power switch means and one of the plurality of second power switch means, both of which power switch means are associated with the respective load.
Claim 12
Dependent Claim
27 words
An interface constructed in accordance with claim 8 wherein the inhibit means includes means inhibiting the operation of both power switch means associated with the respective load.
Claim 13
Dependent Claim
22 words
An interface constructed in accordance with claim 9 wherein the inhibit means includes means inhibiting the operation of all power switch means.
Claim 14
Dependent Claim
17 words
An interface constructed in accordance with claim 11 wherein said substantially fixed reference level is electrical ground.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-04-11 | 1986-10-11 | 1987-04-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-04-11 | 1990-10-11 | 1991-04-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-04-11 | 1994-10-11 | 1995-04-12 | $7700.00 | Window Closed / Lapsed |