US4379347A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Receiver for PCM-encoded multifrequency dialing signals
Assignee: Telecom Italia SpA
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Filing: 1980-11-03
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Granted: 1983-04-05
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Expires: 2000-11-03
Abstract
Abstract To decode multifrequency dialing signals transmitted by a pushbutton-equipped subscriber station of a telecommunication system and quantized upon arrival at a central office, a receiver at the office includes two digital filters separating the incoming binary-coded samples from sine waves in a higher and a lower frequency range and supplying the respective sets of samples to two interpolators converting them into respective square waves fed to a decoder. Each interpolator comprises a sign-bit extractor and an arithmetic unit which emits a numerical value--based on the absolute values of two consecutive samples--representing a delay expressed as a number of clock pulses recurring at a multiple of the sampling rate. A logic network responds to a polarity change of the corresponding sine wave, as determined by the sign-bit extractor, to start a clock-pulse counter measuring a corrective time interval by which the resulting square wave must be delayed so that its pulse flanks substantially coincide with the zero crossings of the sine wave shifted by one sampling period. The delay is accomplished by an Exclusive-OR gate with inputs connected to the logic network and to the sign-bit extractor.
Inventors
- 👤 Guglielmo Girardi
- 👤 Franco Miroglio
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 05:17
CPC Classifications
H; H04; H04Q; H04Q1/00; H04Q1/18; H04Q1/30; H04Q1/44; H04Q1/444; H04Q1/45; H04Q1/457; H04Q1/4575
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
228 words
A receiver for periodically recurring quantized signal samples of a sine wave, each signal sample occurring during a predetermined sampling period substantially shorter than a half-cycle of said sine wave and including a sign bit and a predetermined number of amplitude bits, comprising: a sign-bit extractor connected to an incoming-signal path for converting the sign bits of consecutive signal samples into a square wave with rising and falling pulse flanks subjected to delays of up to one sampling period with reference to an incoming sine wave; interpolation means including a zero-crossing detector controlled by said sign-bit extractor and further including amplitude-bit-extraction means connected to said incoming-signal path for establishing a corrective time interval equal to a fraction of a sampling period in response to any detected sign change, the magnitude of said fraction being determined by the values of two consecutive signal samples having different sign bits; logical circuitry connected to outputs of said sign-bit extractor and of said interpolation means for delaying by said time interval the generation of a pulse flank beyond the instant of appearance of the second one of said consecutive signal samples to separate the time of generation of such a pulse flank by substantially a whole sampling period from the occurrence of the corresponding zero crossing; and decoding means connected to said logical circuitry for converting said square wave into numerical information.
Claim 2
Dependent Claim
228 words
A receiver for periodically recurring quantized signal samples of a sine wave, each signal sample occurring during a predetermined sampling period substantially shorter than a half-cycle of said sine wave and including a sign bit and a predetermined number of amplitude bits, comprising: a sign-bit extractor connected to an incoming-signal path for converting the sign bits of consecutive signal samples into a square wave with rising and falling pulse flanks subjected to delays of up to one sampling period with reference to an incoming sine wave; interpolation means including a zero-crossing detector controlled by said sign-bit extractor and further including amplitude-bit-extraction means connected to said incoming-signal path for establishing a corrective time interval equal to a fraction of a sampling period in response to any detected sign change, the magnitude of said fraction being determined by the values of two consecutive signal samples having different sign bits; logical circuitry connected to outputs of said sign-bit extractor and of said interpolation means for delaying by said time interval the generation of a pulse flank beyond the instant of appearance of the second one of said consecutive signal samples to separate the time of generation of such a pulse flank by substantially a whole sampling period from the occurrence of the corresponding zero crossing; and decoding means connected to said logical circuitry for converting said square wave into numerical information.
Claim 3
Dependent Claim
124 words
A receiver as defined in claim 1 wherein said amplitude-bit-extraction means comprises a first extractor directly connected to said incoming-signal path and a second extractor connected to said incoming-signal path via a digital store delaying incoming signal samples by one sampling period, said interpolation means further comprising an arithmetic unit with inputs respectively connected to outputs of said first and second extractors for deriving from amplitude bits of an undelayed and a delayed sample a ratio R=|x n-1 |/(|x n |+|x n-1 |), where |x n | is the absolute magnitude of the undelayed sample and |x n-1 | is the absolute magnitude of the delayed sample, and timing means connected to said arithmetic unit for translating said ratio into said corrective time interval.
Claim 4
Dependent Claim
111 words
A receiver as defined in claim 2 wherein said timing means includes a source of N clock pulses per sampling period with N >>1, a counter steppable by said clock pulses, a comparator with inputs connected to said counter and to said arithmetic unit for detecting a match between the reading of said counter and a numerical value equal to the integral part of the product R·N emitted by said arithmetic unit, and a logic network responsive to said comparator and to said zero-crossing detector for activating said counter upon the occurrence of a sign change and generating a corrective signal as long as said reading differs from said numerical value.
Claim 5
Dependent Claim
27 words
A receiver as defined in claim 3 wherein said logical circuitry comprises an Exclusive-OR gate with inputs connected to said sign-bit extractor and to said logic network.
Claim 6
Dependent Claim
55 words
A receiver as defined in claim 1, 2, 3 or 4, further comprising digital filter means in said incoming-signal path for directing signal samples from sine wave in different frequency ranges to respective branch paths extending to said decoding means; said sign-bit extractor, logical circuitry and interpolation means being duplicated in all said branch paths.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-04-04 | 1986-10-04 | 1987-04-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-04-04 | 1990-10-04 | 1991-04-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-04-04 | 1994-10-04 | 1995-04-05 | $7700.00 | Window Closed / Lapsed |