US4377844A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Address translator
Assignee: Individual
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Filing: 1980-02-20
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Granted: 1983-03-22
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Expires: 2000-02-20
Abstract
Abstract A memory addressing apparatus (1,20,90) is described comprising a circuit (5,26,96) responsive to a current external memory address on an input line (2,21,91) and a signal generated by an auxiliary memory circuit (8,29,93) for providing a current internal address for addressing an internal memory (15,19,101). For maximum program security, the above described components are all located in a single integrated circuit package.
Inventors
- 👤 Marc Kaufman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 08:27
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0615; G06F12/0623
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
118 words
A memory translating apparatus comprising: means for coupling said apparatus to an external source of memory addresses and an external memory; means storing a predetermined sequence of memory addresses; means responsive to said predetermined sequence and a signal corresponding to a first memory address received from said source, said first memory address from said source being a first memory address in said sequence, for providing an output corresponding to the next memory address in said sequence following said first memory address in said sequence; and means responsive to said output and a second memory address from said external source for addressing said external memory when said second memory address corresponds to said next memory address in said sequence.
Claim 2
Dependent Claim
118 words
A memory translating apparatus comprising: means for coupling said apparatus to an external source of memory addresses and an external memory; means storing a predetermined sequence of memory addresses; means responsive to said predetermined sequence and a signal corresponding to a first memory address received from said source, said first memory address from said source being a first memory address in said sequence, for providing an output corresponding to the next memory address in said sequence following said first memory address in said sequence; and means responsive to said output and a second memory address from said external source for addressing said external memory when said second memory address corresponds to said next memory address in said sequence.
Claim 3
Dependent Claim
42 words
An apparatus according to claim 1 comprising means for detecting a starting memory address from said source and means responsive to said detecting means for providing an initial address for addressing said external memory when a starting external memory address is detected.
Claim 4
Dependent Claim
18 words
An apparatus according to claim 1 wherein said storing and output providing means comprises an auxiliary memory circuit.
Claim 5
Dependent Claim
48 words
An apparatus according to claim 3 wherein said output providing means comprises a plurality of register means, means for selectively storing a signal corresponding to said next address from said auxiliary memory circuit means in said register means; and means for selecting the contents of said register means.
Claim 6
Dependent Claim
132 words
A memory translating apparatus comprising: means for coupling said apparatus to an external source of memory addresses and an external memory; means storing information corresponding to a predetermined sequence of memory addresses from said external source of memory addresses; means responsive to said information in said storing means and a signal corresponding to a first memory address received from said external source of memory addresses for providing an output corresponding to a memory address following said first memory address in said stored predetermined sequence of memory addresses; and means responsive to said output and a second memory address from said external source of memory addresses for addressing said external memory when said second memory address from said external source of memory addresses corresponds to said next memory address in said predetermined sequence.
Claim 7
Dependent Claim
132 words
A memory translating apparatus comprising: means for coupling said apparatus to an external source of memory addresses and an external memory; means storing information corresponding to a predetermined sequence of memory addresses from said external source of memory addresses; means responsive to said information in said storing means and a signal corresponding to a first memory address received from said external source of memory addresses for providing an output corresponding to a memory address following said first memory address in said stored predetermined sequence of memory addresses; and means responsive to said output and a second memory address from said external source of memory addresses for addressing said external memory when said second memory address from said external source of memory addresses corresponds to said next memory address in said predetermined sequence.
Claim 8
Dependent Claim
132 words
A memory translating apparatus comprising: means for coupling said apparatus to an external source of memory addresses and an external memory; means storing information corresponding to a plurality of predetermined sequences of memory addresses which is responsive to a signal corresponding to a memory address previously received from said external source of memory addresses for providing an output corresponding to the next memory address following said previously received memory address in said plurality of sequences of memory addresses; and means responsive to said output and a memory address received from said source of external memory addresses for providing a memory address to address said external memory when said memory address received from said source of external memory addresses corresponds to said next memory address in said plurality of sequences of memory addresses.
Claim 9
Dependent Claim
132 words
A memory translating apparatus comprising: means for coupling said apparatus to an external source of memory addresses and an external memory; means storing information corresponding to a plurality of predetermined sequences of memory addresses which is responsive to a signal corresponding to a memory address previously received from said external source of memory addresses for providing an output corresponding to the next memory address following said previously received memory address in said plurality of sequences of memory addresses; and means responsive to said output and a memory address received from said source of external memory addresses for providing a memory address to address said external memory when said memory address received from said source of external memory addresses corresponds to said next memory address in said plurality of sequences of memory addresses.
Claim 10
Dependent Claim
145 words
A memory address translating apparatus comprising: a means for coupling said apparatus to an external source of memory addresses and an external memory; means for providing a signal corresponding to a memory address previously received from said external source of memory addresses; means for storing information corresponding to a plurality of predetermined sequences of memory addresses; means responsive to said signal and said information in said storing means for providing an output corresponding to the next memory address following said previously received memory address in said plurality of sequences of memory addresses; means responsive to said output and a memory address received from said source of external memory addresses for providing a memory address for addressing said external memory when said memory address received from said source of external memory addresses corresponds to said next-usable memory address in said plurality of sequences of memory addresses.
Claim 11
Dependent Claim
145 words
A memory address translating apparatus comprising: a means for coupling said apparatus to an external source of memory addresses and an external memory; means for providing a signal corresponding to a memory address previously received from said external source of memory addresses; means for storing information corresponding to a plurality of predetermined sequences of memory addresses; means responsive to said signal and said information in said storing means for providing an output corresponding to the next memory address following said previously received memory address in said plurality of sequences of memory addresses; means responsive to said output and a memory address received from said source of external memory addresses for providing a memory address for addressing said external memory when said memory address received from said source of external memory addresses corresponds to said next-usable memory address in said plurality of sequences of memory addresses.
Claim 12
Independent Claim
165 words
A method of addressing a program in an external memory using addresses from an external source of memory addresses comprising the steps of: coupling to said external source of memory addresses and said external memory an apparatus comprising an internal memory; storing a predetermined sequence of the memory addresses of said program in said internal memory; providing external addresses from said source to said apparatus; reading succeeding addresses in said predetermined sequence in response to succeeding addresses received from said external source; providing, in response to a first address in said predetermined sequence and a signal corresponding to a first memory address received from said source, an output corresponding to the next memory address in said sequence following said first memory address in said sequence; and providing, in response to said output and a second memory address received from said source, an address for addressing said external memory when said second memory address from said source corresponds to said next memory address in said sequence.
Claim 13
Independent Claim
165 words
A method of addressing a program in an external memory using addresses from an external source of memory addresses comprising the steps of: coupling to said external source of memory addresses and said external memory an apparatus comprising an internal memory; storing a predetermined sequence of the memory addresses of said program in said internal memory; providing external addresses from said source to said apparatus; reading succeeding addresses in said predetermined sequence in response to succeeding addresses received from said external source; providing, in response to a first address in said predetermined sequence and a signal corresponding to a first memory address received from said source, an output corresponding to the next memory address in said sequence following said first memory address in said sequence; and providing, in response to said output and a second memory address received from said source, an address for addressing said external memory when said second memory address from said source corresponds to said next memory address in said sequence.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-03-21 | 1986-09-20 | 1987-03-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-03-21 | 1990-09-20 | 1991-03-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-03-21 | 1994-09-20 | 1995-03-22 | $7700.00 | Window Closed / Lapsed |